[PATCH] D80175: [PowerPC][MachineCombiner] reassociate fma to expose more ILP

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

I did not look at the patch itself except to notice that it is a lot of code...so I have to ask - did you look at implementing at least the 1st pattern in DAGCombiner? That seems like a general improvement for any superscalar micro-arch with no register pressure disadvantage.



================
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:313-319
+//   A =  FADD X,  Y          (Leaf)
+//   B =  FMA  A,  M21,  M22  (Prev)
+//   C =  FMA  B,  M31,  M32  (Root)
+// -->
+//   A =  FMA  X,  M21,  M22
+//   B =  FMA  Y,  M31,  M32
+//   C =  FADD A,  B
----------------
I was confused here because I was expecting the C++ style notation for FMA (X*Y+Z):
https://en.cppreference.com/w/cpp/numeric/math/fma


Repository:
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  https://reviews.llvm.org/D80175/new/

https://reviews.llvm.org/D80175