[PATCH] D80636: [AMDGPU][MC] Corrected v_writelane_b32 to fix a decoding bug

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp created this revision.
dp added reviewers: arsenm, rampitec.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.
dp added a parent revision: D80637: [AMDGPU][MC][DISASSEMBLER] Corrected decoder to consume each code fragment once.

v_writelane_b32 is defined so that vdst and vdst_in operand types do not match. This result in incorrect decoding of v_writelane_b32 with dst=v255.

See bug 45193 <https://bugs.llvm.org/show_bug.cgi?id=45193>.


https://reviews.llvm.org/D80636

Files:
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt


Index: llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
@@ -98025,7 +98025,7 @@
 # GFX10: v_trunc_f64_e64 v[5:6], |v[1:2]| ; encoding: [0x05,0x01,0x97,0xd5,0x01,0x01,0x00,0x00]
 0x05,0x01,0x97,0xd5,0x01,0x01,0x00,0x00
 
-# GFX10-FIXME: v_writelane_b32 v255, 0, s2     ; encoding: [0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
+# GFX10: v_writelane_b32 v255, 0, s2     ; encoding: [0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
 0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00
 
 # GFX10: v_writelane_b32 v5, -1, s2      ; encoding: [0x05,0x00,0x61,0xd7,0xc1,0x04,0x00,0x00]
Index: llvm/lib/Target/AMDGPU/VOP3Instructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -826,9 +826,9 @@
 
 defm V_READLANE_B32  : VOP3_Real_gfx10<0x360>;
 
-let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in {
+let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
   defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>;
-} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in)
+} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
 
 defm V_XOR3_B32           : VOP3_Real_gfx10<0x178>;
 defm V_LSHLREV_B64        : VOP3_Real_gfx10<0x2ff>;
Index: llvm/lib/Target/AMDGPU/VOP2Instructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1253,9 +1253,9 @@
 
 defm V_READLANE_B32 : VOP2Only_Real_gfx6_gfx7<0x001>;
 
-let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in {
+let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
   defm V_WRITELANE_B32 : VOP2Only_Real_gfx6_gfx7<0x002>;
-} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in)
+} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
 
 let SubtargetPredicate = isGFX6GFX7 in {
   defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;


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