[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

Victor Campos via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 27 08:05:40 PDT 2020


vhscampos updated this revision to Diff 266545.
vhscampos added a comment.

Improve the testcase which exercises loads and stores from stack. Now, wrong frame index replacements will be caught here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072

Files:
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/test/CodeGen/ARM/i64_volatile_load_store.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D70072.266545.patch
Type: text/x-patch
Size: 23531 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200527/130c91f4/attachment-0001.bin>


More information about the llvm-commits mailing list