[llvm] c7593b0 - [ARM] Fix rewrite of frame index in Thumb2's address mode i8s4

[Victor Campos via llvm-commits]

Author: Victor Campos
Date: 2020-05-27T13:09:13+01:00
New Revision: c7593b0f0d28f6b7f9fa4557ce73197a49b37799

URL: https://github.com/llvm/llvm-project/commit/c7593b0f0d28f6b7f9fa4557ce73197a49b37799
DIFF: https://github.com/llvm/llvm-project/commit/c7593b0f0d28f6b7f9fa4557ce73197a49b37799.diff

LOG: [ARM] Fix rewrite of frame index in Thumb2's address mode i8s4

Summary:
In Thumb2's frame index rewriting process, the address mode i8s4, which
is used by LDRD and STRD instructions, is handled by taking the
immediate offset operand and multiplying it by 4.

This behaviour is wrong, however. In this specific address mode, the
MachineInstr's immediate operand is already in the expected form. By
consequence of that, multiplying it once more by 4 yields a flawed
offset value, four times greater than it should be.

Differential Revision: https://reviews.llvm.org/D80557

Added: 
    llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir

Modified: 
    llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 17b2c3584751..48c6b47f2154 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -634,7 +634,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
       assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");
       (void)OffsetMask; // squash unused-variable warning at -NDEBUG
     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
-      Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
+      Offset += MI.getOperand(FrameRegIdx + 1).getImm();
       NumBits = 8 + 2;
       // MCInst operand expects already scaled value.
       Scale = 1;

diff  --git a/llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir b/llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir
new file mode 100644
index 000000000000..0d246ffba722
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -run-pass=prologepilog | FileCheck %s
+--- |
+  ; Function Attrs: noinline nounwind optnone
+  define dso_local i64 @f() #0 {
+  entry:
+    %a = alloca [10 x i64], align 8
+    %arrayidx = getelementptr inbounds [10 x i64], [10 x i64]* %a, i32 0, i32 1
+    store volatile i64 1, i64* %arrayidx, align 8
+    %arrayidx1 = getelementptr inbounds [10 x i64], [10 x i64]* %a, i32 0, i32 1
+    %0 = load volatile i64, i64* %arrayidx1, align 8
+    ret i64 %0
+  }
+
+...
+---
+name:            f
+alignment:       2
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    8
+  maxCallFrameSize: 0
+  localFrameSize:  80
+stack:
+  - { id: 0, name: a, size: 80, alignment: 8, local-offset: -80 }
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: f
+    ; CHECK: $sp = frame-setup tSUBspi $sp, 20, 14 /* CC::al */, $noreg
+    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 80
+    ; CHECK: renamable $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+    ; CHECK: renamable $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
+    ; CHECK: t2STRDi8 killed $r1, killed $r0, $sp, 8, 14 /* CC::al */, $noreg :: (volatile store 8 into %ir.arrayidx)
+    ; CHECK: $r0, $r1 = t2LDRDi8 $sp, 8, 14 /* CC::al */, $noreg :: (volatile dereferenceable load 8 from %ir.arrayidx1)
+    ; CHECK: $sp = frame-destroy tADDspi $sp, 20, 14 /* CC::al */, $noreg
+    ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
+    renamable $r0 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
+    renamable $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
+    t2STRDi8 killed $r1, killed $r0, %stack.0.a, 8, 14 /* CC::al */, $noreg :: (volatile store 8 into %ir.arrayidx)
+    $r0, $r1 = t2LDRDi8 %stack.0.a, 8, 14 /* CC::al */, $noreg :: (volatile dereferenceable load 8 from %ir.arrayidx1)
+    tBX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
+
+...