[PATCH] D80617: [PowerPC] Exploit vnmsubfp instruction

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: hfinkel, jsji, nemanjai, steven.zhang, PowerPC.
Herald added subscribers: llvm-commits, shchenz, kbarton, hiraditya.
Herald added a project: LLVM.
qiucf added a parent revision: D76585: [PowerPC] Require NSZ flag for c-a*b to FNMSUB.
Herald added a subscriber: wuzish.

On PowerPC, we have `vnmsubfp` Altivec instruction for `fnmsub` operation on `v4f32` type. Default pattern for this instruction never works since we don't have legal `fneg` for `v4f32` when VSX disabled.

This is based on new opcodes D76585 <https://reviews.llvm.org/D76585> added.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80617

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/test/CodeGen/PowerPC/fma-negate.ll
  llvm/test/CodeGen/PowerPC/recipest.ll


Index: llvm/test/CodeGen/PowerPC/recipest.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/recipest.ll
+++ llvm/test/CodeGen/PowerPC/recipest.ll
@@ -679,12 +679,9 @@
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    vspltisw 4, -1
 ; CHECK-P7-NEXT:    vrefp 5, 3
-; CHECK-P7-NEXT:    vspltisb 0, -1
-; CHECK-P7-NEXT:    vslw 0, 0, 0
 ; CHECK-P7-NEXT:    vslw 4, 4, 4
-; CHECK-P7-NEXT:    vsubfp 3, 0, 3
 ; CHECK-P7-NEXT:    vmaddfp 4, 2, 5, 4
-; CHECK-P7-NEXT:    vmaddfp 2, 3, 4, 2
+; CHECK-P7-NEXT:    vnmsubfp 2, 3, 4, 2
 ; CHECK-P7-NEXT:    vmaddfp 2, 5, 2, 4
 ; CHECK-P7-NEXT:    blr
 ;
Index: llvm/test/CodeGen/PowerPC/fma-negate.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/fma-negate.ll
+++ llvm/test/CodeGen/PowerPC/fma-negate.ll
@@ -304,10 +304,7 @@
 ;
 ; NO-VSX-LABEL: test_fast_neg_fma_v4f32:
 ; NO-VSX:       # %bb.0: # %entry
-; NO-VSX-NEXT:    vspltisb 5, -1
-; NO-VSX-NEXT:    vslw 5, 5, 5
-; NO-VSX-NEXT:    vsubfp 2, 5, 2
-; NO-VSX-NEXT:    vmaddfp 2, 2, 3, 4
+; NO-VSX-NEXT:    vnmsubfp 2, 2, 3, 4
 ; NO-VSX-NEXT:    blr
                                             <4 x float> %c) {
 entry:
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1031,6 +1031,8 @@
           (VMADDFP $A, $B, $C)>;
 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
           (VNMSUBFP $A, $B, $C)>;
+def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C),
+          (VNMSUBFP $A, $B, $C)>;
 
 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
           (VMADDFP $A, $B, $C)>;
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -16267,8 +16267,7 @@
   SDLoc Loc(N);
 
   // TODO: QPX subtarget is deprecated. No transformation here.
-  if (Subtarget.hasQPX() || !isOperationLegal(ISD::FMA, VT) ||
-      (VT.isVector() && !Subtarget.hasVSX()))
+  if (Subtarget.hasQPX() || !isOperationLegal(ISD::FMA, VT))
     return SDValue();
 
   // Allowing transformation to FNMSUB may change sign of zeroes when ab-c=0


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