[PATCH] D80457: AMDGPU/GlobalISel: Fixed handling of non-standard vectors

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:58
+
+  for (unsigned Idx = 1, E = getNumSubRegIndices() - 1; Idx < E; ++Idx) {
+    unsigned Size = getSubRegIdxSize(Idx);
----------------
Should probably put this into its own function with a FIXME that it should be a table produced by tablegen, also with a call_once?


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.h:40
+  /// All elements of the inner vector combined give a full lane mask.
+  std::vector<int16_t> RegSplitParts[16];
+
----------------
std::array?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80457/new/

https://reviews.llvm.org/D80457