[llvm] 8bc03d2 - GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsic
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue May 26 08:48:23 PDT 2020
Author: Matt Arsenault
Date: 2020-05-26T11:48:13-04:00
New Revision: 8bc03d2168241f7b12265e9cd7e4eb7655709f34
URL: https://github.com/llvm/llvm-project/commit/8bc03d2168241f7b12265e9cd7e4eb7655709f34
DIFF: https://github.com/llvm/llvm-project/commit/8bc03d2168241f7b12265e9cd7e4eb7655709f34.diff
LOG: GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsic
Confusingly, these were unrelated and had different semantics. The
G_PTR_MASK instruction predates the llvm.ptrmask intrinsic, but has a
different format. G_PTR_MASK only allows clearing the low bits of a
pointer, and only a constant number of bits. The ptrmask intrinsic
allows an arbitrary mask. Replace G_PTR_MASK to match the intrinsic.
Only selects the cases that look like the old instruction. More work
is needed to select the general case. Also new legalization code is
still needed to deal with the case where the incoming mask size does
not match the pointer size, which has a specified behavior in the
langref.
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
llvm/test/MachineVerifier/test_g_ptrmask.mir
Modified:
llvm/docs/GlobalISel/GenericOpcode.rst
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/include/llvm/Support/TargetOpcodes.def
llvm/include/llvm/Target/GenericOpcodes.td
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AArch64/GlobalISel/select.mir
Removed:
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
################################################################################
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 7c418a0c05c1..6372192c0088 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -287,14 +287,16 @@ typically bytes but this may vary between targets.
There are currently no in-tree targets that use this with addressable units
not equal to 8 bit.
-G_PTR_MASK
+G_PTRMASK
^^^^^^^^^^
-Zero the least significant N bits of a pointer.
+Zero out an arbitrary mask of bits of a pointer. The mask type must be
+an integer, and the number of vector elements must match for all
+operands. This corresponds to :ref:`i_intr_llvm_ptrmask`.
.. code-block:: none
- %1:_(p0) = G_PTR_MASK %0, 3
+ %2:_(p0) = G_PTRMASK %0, %1
G_SMIN, G_SMAX, G_UMIN, G_UMAX
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 19f65468791d..0252a324de23 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -453,9 +453,15 @@ class MachineIRBuilder {
const LLT ValueTy,
uint64_t Value);
- /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
+ /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
+ MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
+ const SrcOp &Op1) {
+ return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
+ }
+
+ /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
///
- /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
+ /// This clears the low bits of a pointer operand without destroying its
/// pointer properties. This has the effect of rounding the address *down* to
/// a specified alignment in bits.
///
@@ -466,8 +472,8 @@ class MachineIRBuilder {
/// be cleared in \p Op0.
///
/// \return a MachineInstrBuilder for the newly created instruction.
- MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
- uint32_t NumBits);
+ MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
+ uint32_t NumBits);
/// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
///
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 8385af9de2a4..eae831f3353b 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -556,9 +556,8 @@ HANDLE_TARGET_OPCODE(G_FMAXIMUM)
/// Generic pointer offset
HANDLE_TARGET_OPCODE(G_PTR_ADD)
-/// Clear the specified number of low bits in a pointer. This rounds the value
-/// *down* to the given alignment.
-HANDLE_TARGET_OPCODE(G_PTR_MASK)
+/// Clear the specified bits in a pointer.
+HANDLE_TARGET_OPCODE(G_PTRMASK)
/// Generic signed integer minimum.
HANDLE_TARGET_OPCODE(G_SMIN)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 441f1580dd25..5ba7844c8c9e 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -358,9 +358,11 @@ def G_PTR_ADD : GenericInstruction {
let hasSideEffects = 0;
}
-def G_PTR_MASK : GenericInstruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src, unknown:$bits);
+// Generic pointer mask. type1 should be an integer with the same
+// bitwidth as the pointer type.
+def G_PTRMASK : GenericInstruction {
+ let OutOperandList = (outs ptype0:$dst);
+ let InOperandList = (ins ptype0:$src, type1:$bits);
let hasSideEffects = 0;
}
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index eba352aedb07..df965e466698 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1281,6 +1281,8 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
return TargetOpcode::G_INTRINSIC_TRUNC;
case Intrinsic::readcyclecounter:
return TargetOpcode::G_READCYCLECOUNTER;
+ case Intrinsic::ptrmask:
+ return TargetOpcode::G_PTRMASK;
}
return Intrinsic::not_intrinsic;
}
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 7af8332bbce3..510572e6d412 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -237,17 +237,14 @@ MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0,
return buildPtrAdd(Res, Op0, Cst.getReg(0));
}
-MachineInstrBuilder MachineIRBuilder::buildPtrMask(const DstOp &Res,
- const SrcOp &Op0,
- uint32_t NumBits) {
- assert(Res.getLLTTy(*getMRI()).isPointer() &&
- Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
-
- auto MIB = buildInstr(TargetOpcode::G_PTR_MASK);
- Res.addDefToMIB(*getMRI(), MIB);
- Op0.addSrcToMIB(MIB);
- MIB.addImm(NumBits);
- return MIB;
+MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res,
+ const SrcOp &Op0,
+ uint32_t NumBits) {
+ LLT PtrTy = Res.getLLTTy(*getMRI());
+ LLT MaskTy = LLT::scalar(PtrTy.getSizeInBits());
+ Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy);
+ buildConstant(MaskReg, maskTrailingOnes<uint64_t>(NumBits));
+ return buildPtrMask(Res, Op0, MaskReg);
}
MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index f626c1291607..f07856d799c9 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1102,6 +1102,22 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
// TODO: Is the offset allowed to be a scalar with a vector?
break;
}
+ case TargetOpcode::G_PTRMASK: {
+ LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+ LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
+ LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
+ if (!DstTy.isValid() || !SrcTy.isValid() || !MaskTy.isValid())
+ break;
+
+ if (!DstTy.getScalarType().isPointer())
+ report("ptrmask result type must be a pointer", MI);
+
+ if (!MaskTy.getScalarType().isScalar())
+ report("ptrmask mask type must be an integer", MI);
+
+ verifyVectorElementMatch(DstTy, MaskTy, MI);
+ break;
+ }
case TargetOpcode::G_SEXT:
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_ANYEXT:
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 5789d1d2531c..57eaf140a638 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -2383,14 +2383,17 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
return true;
}
- case TargetOpcode::G_PTR_MASK: {
- uint64_t Align = I.getOperand(2).getImm();
- if (Align >= 64 || Align == 0)
+ case TargetOpcode::G_PTRMASK: {
+ Register MaskReg = I.getOperand(2).getReg();
+ Optional<int64_t> MaskVal = getConstantVRegVal(MaskReg, MRI);
+ // TODO: Implement arbitrary cases
+ if (!MaskVal || !isShiftedMask_64(*MaskVal))
return false;
- uint64_t Mask = ~((1ULL << Align) - 1);
+ uint64_t Mask = *MaskVal;
I.setDesc(TII.get(AArch64::ANDXri));
- I.getOperand(2).setImm(AArch64_AM::encodeLogicalImmediate(Mask, 64));
+ I.getOperand(2).ChangeToImmediate(
+ AArch64_AM::encodeLogicalImmediate(Mask, 64));
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
index 4378f5dbd8f9..3caa9026c9d8 100644
--- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -108,7 +108,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
.legalFor({{p0, s64}})
.clampScalar(1, s64, s64);
- getActionDefinitionsBuilder(G_PTR_MASK).legalFor({p0});
+ getActionDefinitionsBuilder(G_PTRMASK).legalFor({{p0, s64}});
getActionDefinitionsBuilder({G_SDIV, G_UDIV})
.legalFor({s32, s64})
@@ -744,7 +744,7 @@ bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
auto AlignMinus1 =
MIRBuilder.buildConstant(IntPtrTy, Alignment.value() - 1);
auto ListTmp = MIRBuilder.buildPtrAdd(PtrTy, List, AlignMinus1.getReg(0));
- DstPtr = MIRBuilder.buildPtrMask(PtrTy, ListTmp, Log2(Alignment));
+ DstPtr = MIRBuilder.buildMaskLowPtrBits(PtrTy, ListTmp, Log2(Alignment));
} else
DstPtr = List;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 242a108f156c..e47f25f7828d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -2231,9 +2231,14 @@ bool AMDGPUInstructionSelector::selectG_FRAME_INDEX_GLOBAL_VALUE(
DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI);
}
-bool AMDGPUInstructionSelector::selectG_PTR_MASK(MachineInstr &I) const {
- uint64_t Align = I.getOperand(2).getImm();
- const uint64_t Mask = ~((UINT64_C(1) << Align) - 1);
+bool AMDGPUInstructionSelector::selectG_PTRMASK(MachineInstr &I) const {
+ Register MaskReg = I.getOperand(2).getReg();
+ Optional<int64_t> MaskVal = getConstantVRegVal(MaskReg, *MRI);
+ // TODO: Implement arbitrary cases
+ if (!MaskVal || !isShiftedMask_64(*MaskVal))
+ return false;
+
+ const uint64_t Mask = *MaskVal;
MachineBasicBlock *BB = I.getParent();
@@ -2731,8 +2736,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
case TargetOpcode::G_FRAME_INDEX:
case TargetOpcode::G_GLOBAL_VALUE:
return selectG_FRAME_INDEX_GLOBAL_VALUE(I);
- case TargetOpcode::G_PTR_MASK:
- return selectG_PTR_MASK(I);
+ case TargetOpcode::G_PTRMASK:
+ return selectG_PTRMASK(I);
case TargetOpcode::G_EXTRACT_VECTOR_ELT:
return selectG_EXTRACT_VECTOR_ELT(I);
case TargetOpcode::G_INSERT_VECTOR_ELT:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
index 3e3a3d8326c2..0ac6788c69b8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
@@ -130,7 +130,7 @@ class AMDGPUInstructionSelector : public InstructionSelector {
bool selectG_SELECT(MachineInstr &I) const;
bool selectG_BRCOND(MachineInstr &I) const;
bool selectG_FRAME_INDEX_GLOBAL_VALUE(MachineInstr &I) const;
- bool selectG_PTR_MASK(MachineInstr &I) const;
+ bool selectG_PTRMASK(MachineInstr &I) const;
bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 63106df9e2a2..c24996b93fa0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -560,7 +560,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.scalarize(0);
}
- getActionDefinitionsBuilder({G_PTR_ADD, G_PTR_MASK})
+ getActionDefinitionsBuilder(G_PTR_ADD)
+ .scalarize(0)
+ .alwaysLegal();
+
+ // TODO: Clamp mask to pointer sizes
+ getActionDefinitionsBuilder(G_PTRMASK)
.scalarize(0)
.alwaysLegal();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 1cfc7ccc6cb7..f11563a66d41 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3228,6 +3228,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
LLVM_FALLTHROUGH;
}
case AMDGPU::G_PTR_ADD:
+ case AMDGPU::G_PTRMASK:
case AMDGPU::G_ADD:
case AMDGPU::G_SUB:
case AMDGPU::G_MUL:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
index 7446fde7ba08..a0cc56677118 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
@@ -15,17 +15,18 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s64)
- ; CHECK: G_STORE [[GEP]](p0), [[COPY]](p0) :: (store 8)
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C]](s64)
+ ; CHECK: G_STORE [[PTR_ADD]](p0), [[COPY]](p0) :: (store 8)
; CHECK: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
- ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD1]], [[C]](s64)
- ; CHECK: G_STORE [[GEP1]](p0), [[COPY]](p0) :: (store 8)
+ ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD1]], [[C]](s64)
+ ; CHECK: G_STORE [[PTR_ADD1]](p0), [[COPY]](p0) :: (store 8)
; CHECK: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD2]], [[C1]](s64)
- ; CHECK: [[PTR_MASK:%[0-9]+]]:_(p0) = G_PTR_MASK [[GEP2]], 4
- ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_MASK]], [[C]](s64)
- ; CHECK: G_STORE [[GEP3]](p0), [[COPY]](p0) :: (store 8)
+ ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD2]], [[C1]](s64)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
+ ; CHECK: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD2]], [[COPY1]](s64)
+ ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C]](s64)
+ ; CHECK: G_STORE [[PTR_ADD3]](p0), [[COPY]](p0) :: (store 8)
%0:_(p0) = COPY $x0
%1:_(s8) = G_VAARG %0(p0), 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 1b63f672aabe..4a68d09c545a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -441,8 +441,8 @@
# DEBUG-NEXT: G_PTR_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
-# DEBUG-NEXT: G_PTR_MASK (opcode {{[0-9]+}}): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: G_PTRMASK (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG: G_SMIN (opcode {{[0-9]+}}): 1 type index
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
index 2e38f1ce62e9..ca4091180b1a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -125,12 +125,13 @@ legalized: true
regBankSelected: true
# CHECK: body:
-# CHECK: %1:gpr64sp = ANDXri %0, 8060
+# CHECK: %2:gpr64sp = ANDXri %0, 8060
body: |
bb.0:
liveins: $x0
%0:gpr(p0) = COPY $x0
- %1:gpr(p0) = G_PTR_MASK %0, 3
+ %const:gpr(s64) = G_CONSTANT i64 -8
+ %1:gpr(p0) = G_PTRMASK %0, %const
$x0 = COPY %1(p0)
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
deleted file mode 100644
index fcc9565ce9ee..000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir
+++ /dev/null
@@ -1,475 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
-
----
-name: ptr_mask_p3_sgpr_sgpr_1
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_1
- ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
- %0:sgpr(p3) = COPY $sgpr0
- %1:sgpr(p3) = G_PTR_MASK %0, 1
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_sgpr_sgpr_2
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_2
- ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
- %0:sgpr(p3) = COPY $sgpr0
- %1:sgpr(p3) = G_PTR_MASK %0, 2
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_sgpr_sgpr_3
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_3
- ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
- %0:sgpr(p3) = COPY $sgpr0
- %1:sgpr(p3) = G_PTR_MASK %0, 3
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_sgpr_sgpr_4
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_4
- ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
- %0:sgpr(p3) = COPY $sgpr0
- %1:sgpr(p3) = G_PTR_MASK %0, 4
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_sgpr_sgpr_29
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_29
- ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
- %0:sgpr(p3) = COPY $sgpr0
- %1:sgpr(p3) = G_PTR_MASK %0, 4
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_sgpr_sgpr_1
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_1
- ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2
- ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:sgpr(p0) = COPY $sgpr0_sgpr1
- %1:sgpr(p0) = G_PTR_MASK %0, 1
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_sgpr_sgpr_2
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_2
- ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
- ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:sgpr(p0) = COPY $sgpr0_sgpr1
- %1:sgpr(p0) = G_PTR_MASK %0, 2
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_sgpr_sgpr_3
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_3
- ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
- ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:sgpr(p0) = COPY $sgpr0_sgpr1
- %1:sgpr(p0) = G_PTR_MASK %0, 3
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_sgpr_sgpr_4
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_4
- ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
- ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:sgpr(p0) = COPY $sgpr0_sgpr1
- %1:sgpr(p0) = G_PTR_MASK %0, 4
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_sgpr_sgpr_29
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_29
- ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
- ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
- ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:sgpr(p0) = COPY $sgpr0_sgpr1
- %1:sgpr(p0) = G_PTR_MASK %0, 4
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_vgpr_vgpr_1
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_1
- ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
- %0:vgpr(p3) = COPY $vgpr0
- %1:vgpr(p3) = G_PTR_MASK %0, 1
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_vgpr_vgpr_2
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_2
- ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
- %0:vgpr(p3) = COPY $vgpr0
- %1:vgpr(p3) = G_PTR_MASK %0, 2
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_vgpr_vgpr_3
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_3
- ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
- %0:vgpr(p3) = COPY $vgpr0
- %1:vgpr(p3) = G_PTR_MASK %0, 2
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_vgpr_vgpr_4
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_4
- ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
- %0:vgpr(p3) = COPY $vgpr0
- %1:vgpr(p3) = G_PTR_MASK %0, 4
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_vgpr_vgpr_29
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_29
- ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
- %0:vgpr(p3) = COPY $vgpr0
- %1:vgpr(p3) = G_PTR_MASK %0, 4
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_vgpr_vgpr_1
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_1
- ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:vgpr(p0) = COPY $vgpr0_vgpr1
- %1:vgpr(p0) = G_PTR_MASK %0, 1
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_vgpr_vgpr_2
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_2
- ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:vgpr(p0) = COPY $vgpr0_vgpr1
- %1:vgpr(p0) = G_PTR_MASK %0, 2
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_vgpr_vgpr_3
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_3
- ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:vgpr(p0) = COPY $vgpr0_vgpr1
- %1:vgpr(p0) = G_PTR_MASK %0, 2
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_vgpr_vgpr_4
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_4
- ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:vgpr(p0) = COPY $vgpr0_vgpr1
- %1:vgpr(p0) = G_PTR_MASK %0, 4
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_vgpr_vgpr_29
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_29
- ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:vgpr(p0) = COPY $vgpr0_vgpr1
- %1:vgpr(p0) = G_PTR_MASK %0, 4
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p3_vgpr_sgpr_2
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0
-
- ; CHECK-LABEL: name: ptr_mask_p3_vgpr_sgpr_2
- ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
- %0:sgpr(p3) = COPY $sgpr0
- %1:vgpr(p3) = G_PTR_MASK %0, 2
- S_ENDPGM 0, implicit %1
-
-...
-
----
-name: ptr_mask_p0_vgpr_sgpr_2
-legalized: true
-regBankSelected: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
-
- ; CHECK-LABEL: name: ptr_mask_p0_vgpr_sgpr_2
- ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
- ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
- ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
- ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
- ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
- %0:sgpr(p0) = COPY $sgpr0_sgpr1
- %1:vgpr(p0) = G_PTR_MASK %0, 2
- S_ENDPGM 0, implicit %1
-
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
new file mode 100644
index 000000000000..1f8325018af2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
@@ -0,0 +1,800 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: ptrmask_p3_s32_sgpr_sgpr_sgpr
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_sgpr
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p3) = G_PTRMASK [[COPY]], [[COPY1]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p3)
+ %0:sgpr(p3) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(p3) = G_PTRMASK %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
+ ; CHECK: %const:sgpr(s32) = G_CONSTANT i32 -252645136
+ ; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p3) = G_PTRMASK [[COPY]], %const(s32)
+ ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p3)
+ %0:sgpr(p3) = COPY $sgpr0
+ %const:sgpr(s32) = G_CONSTANT i32 -252645136
+ %1:sgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_s32_sgpr_sgpr_clearhi1
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi1
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sgpr(p3) = COPY $sgpr0
+ %const:sgpr(s32) = G_CONSTANT i32 -2147483648
+ %1:sgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_s32_sgpr_sgpr_clearhi2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi2
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1073741824
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sgpr(p3) = COPY $sgpr0
+ %const:sgpr(s32) = G_CONSTANT i32 -1073741824
+ %1:sgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_s32_sgpr_sgpr_clearlo1
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo1
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sgpr(p3) = COPY $sgpr0
+ %const:sgpr(s32) = G_CONSTANT i32 -2
+ %1:sgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_s32_sgpr_sgpr_clearlo2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo2
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sgpr(p3) = COPY $sgpr0
+ %const:sgpr(s32) = G_CONSTANT i32 -4
+ %1:sgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_s32_sgpr_sgpr_clearlo3
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo3
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sgpr(p3) = COPY $sgpr0
+ %const:sgpr(s32) = G_CONSTANT i32 -8
+ %1:sgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_s32_sgpr_sgpr_clearlo4
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo4
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sgpr(p3) = COPY $sgpr0
+ %const:sgpr(s32) = G_CONSTANT i32 -16
+ %1:sgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_s32_sgpr_sgpr_clearlo29
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo29
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -536870912
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
+ %0:sgpr(p3) = COPY $sgpr0
+ %const:sgpr(s32) = G_CONSTANT i32 -536870912
+ %1:sgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_sgpr
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64)
+ ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0)
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = COPY $sgpr2_sgpr3
+ %2:sgpr(p0) = G_PTRMASK %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 -1085102592571150096
+ ; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p0) = G_PTRMASK [[COPY]], [[C]](s64)
+ ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0)
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = G_CONSTANT i64 -1085102592571150096
+ %2:sgpr(p0) = G_PTRMASK %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+name: ptrmask_p0_s32_sgpr_sgpr_sgpr
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; CHECK-LABEL: name: ptrmask_p0_s32_sgpr_sgpr_sgpr
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0)
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %1:sgpr(s32) = COPY $sgpr2
+ %2:sgpr(p0) = G_PTRMASK %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_clearhi1
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi1
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -9223372036854775808
+ ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %const:sgpr(s64) = G_CONSTANT i64 -9223372036854775808
+ %1:sgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_clearhi32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi32
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4294967296
+ ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %const:sgpr(s64) = G_CONSTANT i64 -4294967296
+ %1:sgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_clear_32
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clear_32
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967296
+ ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %const:sgpr(s64) = G_CONSTANT i64 4294967296
+ %1:sgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_clearlo1
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo1
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2
+ ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %const:sgpr(s64) = G_CONSTANT i64 -2
+ %1:sgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_clearlo2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo2
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
+ ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %const:sgpr(s64) = G_CONSTANT i64 -4
+ %1:sgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_clearlo3
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo3
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
+ ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %const:sgpr(s64) = G_CONSTANT i64 -8
+ %1:sgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_clearlo4
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo4
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
+ ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %const:sgpr(s64) = G_CONSTANT i64 -16
+ %1:sgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_sgpr_sgpr_clearlo29
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo29
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -536870912
+ ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
+ ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %const:sgpr(s64) = G_CONSTANT i64 -536870912
+ %1:sgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
+ ; CHECK: %const:vgpr(s32) = G_CONSTANT i32 -252645136
+ ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p3) = G_PTRMASK [[COPY]], %const(s32)
+ ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p3)
+ %0:vgpr(p3) = COPY $vgpr0
+ %const:vgpr(s32) = G_CONSTANT i32 -252645136
+ %1:vgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_vgpr_vgpr_clearlo1
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo1
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
+ %0:vgpr(p3) = COPY $vgpr0
+ %const:vgpr(s32) = G_CONSTANT i32 -2
+ %1:vgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_vgpr_vgpr_clearlo2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo2
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
+ %0:vgpr(p3) = COPY $vgpr0
+ %const:vgpr(s32) = G_CONSTANT i32 -4
+ %1:vgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_vgpr_vgpr_clearlo3
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo3
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -8, implicit $exec
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
+ %0:vgpr(p3) = COPY $vgpr0
+ %const:vgpr(s32) = G_CONSTANT i32 -8
+ %1:vgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_vgpr_vgpr_clearlo4
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo4
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
+ %0:vgpr(p3) = COPY $vgpr0
+ %const:vgpr(s32) = G_CONSTANT i32 -16
+ %1:vgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_vgpr_vgpr_clearlo29
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo29
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -536870912, implicit $exec
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
+ %0:vgpr(p3) = COPY $vgpr0
+ %const:vgpr(s32) = G_CONSTANT i32 -536870912
+ %1:vgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_vgpr_vgpr_vgpr
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64)
+ ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0)
+ %0:vgpr(p0) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vgpr(p0) = G_PTRMASK %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 -1085102592571150096
+ ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], [[C]](s64)
+ ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0)
+ %0:vgpr(p0) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = G_CONSTANT i64 -1085102592571150096
+ %2:vgpr(p0) = G_PTRMASK %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+name: ptrmask_p0_s32_vgpr_vgpr_vgpr
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ ; CHECK-LABEL: name: ptrmask_p0_s32_vgpr_vgpr_vgpr
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
+ ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0)
+ %0:vgpr(p0) = COPY $vgpr0_vgpr1
+ %1:vgpr(s32) = COPY $vgpr2
+ %2:vgpr(p0) = G_PTRMASK %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+name: ptrmask_p0_s64_vgpr_vgpr_clearlo1
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo1
+ ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:vgpr(p0) = COPY $vgpr0_vgpr1
+ %const:vgpr(s64) = G_CONSTANT i64 -2
+ %1:vgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_vgpr_vgpr_clearlo2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo2
+ ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:vgpr(p0) = COPY $vgpr0_vgpr1
+ %const:vgpr(s64) = G_CONSTANT i64 -4
+ %1:vgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_vgpr_vgpr_clearlo3
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo3
+ ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:vgpr(p0) = COPY $vgpr0_vgpr1
+ %const:vgpr(s64) = G_CONSTANT i64 -4
+ %1:vgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_vgpr_vgpr_clearlo4
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo4
+ ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:vgpr(p0) = COPY $vgpr0_vgpr1
+ %const:vgpr(s64) = G_CONSTANT i64 -16
+ %1:vgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_vgpr_vgpr_clearlo29
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo29
+ ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -536870912, implicit $exec
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:vgpr(p0) = COPY $vgpr0_vgpr1
+ %const:vgpr(s64) = G_CONSTANT i64 -536870912
+ %1:vgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p3_vgpr_sgpr_clearlo2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrmask_p3_vgpr_sgpr_clearlo2
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
+ %0:sgpr(p3) = COPY $sgpr0
+ %const:sgpr(s32) = G_CONSTANT i32 -4
+ %1:vgpr(p3) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
+
+---
+name: ptrmask_p0_s64_vgpr_sgpr_clearlo2
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_sgpr_clearlo2
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
+ ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %const:sgpr(s32) = G_CONSTANT i32 -4
+ %1:vgpr(p0) = G_PTRMASK %0, %const
+ S_ENDPGM 0, implicit %1
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
new file mode 100644
index 000000000000..cc1c75e404e0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
@@ -0,0 +1,161 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+
+define i8* @ptrmask_flat_i64(i8* %ptr, i64 %mask) {
+ ; CHECK-LABEL: name: ptrmask_flat_i64
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
+ ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[MV1]](s64)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[UV1]](s32)
+ ; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
+ ; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
+ %masked = call i8* @llvm.ptrmask.p0i8.i64(i8* %ptr, i64 %mask)
+ ret i8* %masked
+}
+
+define i8* @ptrmask_flat_i32(i8* %ptr, i32 %mask) {
+ ; CHECK-LABEL: name: ptrmask_flat_i32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[COPY2]](s32)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[UV1]](s32)
+ ; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
+ ; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0, implicit $vgpr1
+ %masked = call i8* @llvm.ptrmask.p0i8.i32(i8* %ptr, i32 %mask)
+ ret i8* %masked
+}
+
+define i8* @ptrmask_flat_i16(i8* %ptr, i16 %mask) {
+ ; CHECK-LABEL: name: ptrmask_flat_i16
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; CHECK: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[TRUNC]](s16)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[UV1]](s32)
+ ; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
+ ; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0, implicit $vgpr1
+ %masked = call i8* @llvm.ptrmask.p0i8.i16(i8* %ptr, i16 %mask)
+ ret i8* %masked
+}
+
+define i8* @ptrmask_flat_i1(i8* %ptr, i1 %mask) {
+ ; CHECK-LABEL: name: ptrmask_flat_i1
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[MV]], [[TRUNC]](s1)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTRMASK]](p0)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[UV1]](s32)
+ ; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
+ ; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0, implicit $vgpr1
+ %masked = call i8* @llvm.ptrmask.p0i8.i1(i8* %ptr, i1 %mask)
+ ret i8* %masked
+}
+
+define i8 addrspace(3)* @ptrmask_local_i64(i8 addrspace(3)* %ptr, i64 %mask) {
+ ; CHECK-LABEL: name: ptrmask_local_i64
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
+ ; CHECK: [[PTRMASK:%[0-9]+]]:_(p3) = G_PTRMASK [[COPY]], [[MV]](s64)
+ ; CHECK: $vgpr0 = COPY [[PTRMASK]](p3)
+ ; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
+ ; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
+ %masked = call i8 addrspace(3)* @llvm.ptrmask.p3i8.i64(i8 addrspace(3)* %ptr, i64 %mask)
+ ret i8 addrspace(3)* %masked
+}
+
+define i8 addrspace(3)* @ptrmask_local_i32(i8 addrspace(3)* %ptr, i32 %mask) {
+ ; CHECK-LABEL: name: ptrmask_local_i32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[PTRMASK:%[0-9]+]]:_(p3) = G_PTRMASK [[COPY]], [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[PTRMASK]](p3)
+ ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
+ ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
+ %masked = call i8 addrspace(3)* @llvm.ptrmask.p3i8.i32(i8 addrspace(3)* %ptr, i32 %mask)
+ ret i8 addrspace(3)* %masked
+}
+
+define i8 addrspace(3)* @ptrmask_local_i16(i8 addrspace(3)* %ptr, i16 %mask) {
+ ; CHECK-LABEL: name: ptrmask_local_i16
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[PTRMASK:%[0-9]+]]:_(p3) = G_PTRMASK [[COPY]], [[TRUNC]](s16)
+ ; CHECK: $vgpr0 = COPY [[PTRMASK]](p3)
+ ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
+ ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
+ %masked = call i8 addrspace(3)* @llvm.ptrmask.p3i8.i16(i8 addrspace(3)* %ptr, i16 %mask)
+ ret i8 addrspace(3)* %masked
+}
+
+define i8 addrspace(3)* @ptrmask_local_i1(i8 addrspace(3)* %ptr, i1 %mask) {
+ ; CHECK-LABEL: name: ptrmask_local_i1
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[PTRMASK:%[0-9]+]]:_(p3) = G_PTRMASK [[COPY]], [[TRUNC]](s1)
+ ; CHECK: $vgpr0 = COPY [[PTRMASK]](p3)
+ ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
+ ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
+ %masked = call i8 addrspace(3)* @llvm.ptrmask.p3i8.i1(i8 addrspace(3)* %ptr, i1 %mask)
+ ret i8 addrspace(3)* %masked
+}
+
+; Seems to not work
+; define <2 x i8*> @ptrmask_flat_i64_v2(<2 x i8*> %ptr, <2 x i64> %mask) {
+; %masked = call <2 x i8*> @llvm.ptrmask.v2p0i8.v2i64(<2 x i8*> %ptr, <2 x i64> %mask)
+; ret <2 x i8*> %masked
+; }
+
+declare i8* @llvm.ptrmask.p0i8.i64(i8*, i64)
+declare i8* @llvm.ptrmask.p0i8.i32(i8*, i32)
+declare i8* @llvm.ptrmask.p0i8.i16(i8*, i16)
+declare i8* @llvm.ptrmask.p0i8.i1(i8*, i1)
+declare i8 addrspace(3)* @llvm.ptrmask.p3i8.i64(i8 addrspace(3)*, i64)
+declare i8 addrspace(3)* @llvm.ptrmask.p3i8.i32(i8 addrspace(3)*, i32)
+declare i8 addrspace(3)* @llvm.ptrmask.p3i8.i16(i8 addrspace(3)*, i16)
+declare i8 addrspace(3)* @llvm.ptrmask.p3i8.i1(i8 addrspace(3)*, i1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
new file mode 100644
index 000000000000..0449b162968f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
@@ -0,0 +1,90 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: ptrmask_p1_s_k
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p1_s_k
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 1
+ ; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p1) = G_PTRMASK [[COPY]], [[C]](s64)
+ %0:_(p1) = COPY $sgpr0_sgpr1
+ %1:_(s64) = G_CONSTANT i64 1
+ %2:_(p1) = G_PTRMASK %0, %1
+...
+
+---
+name: ptrmask_p1_s_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+
+ ; CHECK-LABEL: name: ptrmask_p1_s_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p1) = G_PTRMASK [[COPY]], [[COPY1]](s64)
+ %0:_(p1) = COPY $sgpr0_sgpr1
+ %1:_(s64) = COPY $sgpr2_sgpr3
+ %2:_(p1) = G_PTRMASK %0, %1
+...
+
+---
+name: ptrmask_p1_v_k
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p1_v_k
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
+ ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p1) = G_PTRMASK [[COPY]], [[COPY1]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_CONSTANT i64 1
+ %2:_(p1) = G_PTRMASK %0, %1
+...
+
+---
+name: ptrmask_p1_v_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrmask_p1_v_s
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
+ ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p1) = G_PTRMASK [[COPY]], [[COPY2]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $sgpr0_sgpr1
+ %2:_(p1) = G_PTRMASK %0, %1
+...
+
+---
+name: ptrmask_p1_v_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: ptrmask_p1_v_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p1) = G_PTRMASK [[COPY]], [[COPY1]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(p1) = G_PTRMASK %0, %1
+...
diff --git a/llvm/test/MachineVerifier/test_g_ptrmask.mir b/llvm/test/MachineVerifier/test_g_ptrmask.mir
new file mode 100644
index 000000000000..6edf1b1d894a
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_g_ptrmask.mir
@@ -0,0 +1,54 @@
+# REQUIRES: aarch64-registered-target
+# RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+
+---
+name: test_ptr_mask
+tracksRegLiveness: true
+liveins:
+body: |
+ bb.0:
+
+ %0:_(p0) = G_IMPLICIT_DEF
+ %1:_(p0) = G_IMPLICIT_DEF
+ %2:_(s64) = G_IMPLICIT_DEF
+
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
+ ; CHECK: Bad machine code: ptrmask result type must be a pointer
+ %3:_(s64) = G_PTRMASK %0, %2
+
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
+ %4:_(p0) = G_PTRMASK %2, %2
+
+ ; CHECK: Bad machine code: ptrmask mask type must be an integer
+ %5:_(p0) = G_PTRMASK %0, %0
+
+ %6:_(<2 x p0>) = G_IMPLICIT_DEF
+ %7:_(<2 x s64>) = G_IMPLICIT_DEF
+
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
+ ; CHECK: Bad machine code: ptrmask result type must be a pointer
+ %8:_(<2 x s64>) = G_PTRMASK %6, %7
+
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
+ %9:_(<2 x p0>) = G_PTRMASK %7, %7
+
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
+ ; CHECK: Bad machine code: ptrmask mask type must be an integer
+ ; CHECK: Bad machine code: operand types must be all-vector or all-scalar
+ %10:_(<2 x p0>) = G_PTRMASK %0, %0
+
+ ; CHECK: Bad machine code: Type mismatch in generic instruction
+ %11:_(p0) = G_PTRMASK %6, %2
+
+ ; CHECK: Bad machine code: operand types must be all-vector or all-scalar
+ %12:_(p0) = G_PTRMASK %0, %7
+
+ ; CHECK: Bad machine code: operand types must be all-vector or all-scalar
+ %13:_(<2 x p0>) = G_PTRMASK %6, %2
+
+ %14:_(<4 x p0>) = G_IMPLICIT_DEF
+
+ ; CHECK: Bad machine code: operand types must preserve number of vector elements
+ %15:_(<4 x p0>) = G_PTRMASK %14, %8
+
+...
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