[PATCH] D80470: AMDGPU: Start adding MODE register uses to instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, nhaehnle, foad, kerbowa.
Herald added subscribers: javed.absar, hiraditya, t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl, qcolombet, MatzeB.
Herald added a project: LLVM.

This is the groundwork required to implement strictfp. For now, this
should be NFC for regular instructions (many instructions just gain an
extra use of a reserved register). Regalloc won't rematerialize
instructions with reads of physical registers, but we were suffering
from that anyway with the exec reads.

Should add it for all the related FP uses (possibly with some
extras). I did not add it to either the gpr index mode instructions
or every single VALU instruction) since it's a ridiculous feature
already modeled as an arbitrary side effect.

      

Also work towards marking instructions with FP exceptions. This
doesn't actually set the bit yet since this would start to change
codegen. It seems nofpexcept is currently not implied from the regular
IR FP operations. Add it to some MIR tests where I think it might
matter.


https://reviews.llvm.org/D80470

Files:
  llvm/lib/Target/AMDGPU/SIInstrFormats.td
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/lib/Target/AMDGPU/VOP1Instructions.td
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/lib/Target/AMDGPU/VOP3PInstructions.td
  llvm/lib/Target/AMDGPU/VOPCInstructions.td
  llvm/lib/Target/AMDGPU/VOPInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
  llvm/test/CodeGen/AMDGPU/bundle-latency.mir
  llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
  llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
  llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
  llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
  llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
  llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
  llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
  llvm/test/CodeGen/AMDGPU/dead-lane.mir
  llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
  llvm/test/CodeGen/AMDGPU/dpp_combine.mir
  llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
  llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
  llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
  llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
  llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
  llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
  llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
  llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
  llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
  llvm/test/CodeGen/AMDGPU/hazard-kill.mir
  llvm/test/CodeGen/AMDGPU/hazard.mir
  llvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir
  llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
  llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
  llvm/test/CodeGen/AMDGPU/mai-hazards.mir
  llvm/test/CodeGen/AMDGPU/merge-m0.mir
  llvm/test/CodeGen/AMDGPU/mode-register.mir
  llvm/test/CodeGen/AMDGPU/movrels-bug.mir
  llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
  llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
  llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
  llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
  llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
  llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
  llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
  llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
  llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
  llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
  llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
  llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
  llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
  llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
  llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
  llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
  llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
  llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
  llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
  llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
  llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
  llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
  llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
  llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
  llvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
  llvm/unittests/MI/LiveIntervalTest.cpp

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