[PATCH] D80364: [amdgpu] Teach load widening to handle non-DWORD aligned loads.

[Michael Liao via Phabricator via llvm-commits]

hliao marked an inline comment as done.
hliao added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:7472-7475
+    std::tie(AD, RC) =
+        MFI->getPreloadedValue(AMDGPUFunctionArgInfo::DISPATCH_PTR);
+    if (AD && AD->isRegister() && AD->getRegister() == Reg)
+      return true;
----------------
hliao wrote:
> hliao wrote:
> > arsenm wrote:
> > > This will be true for all of the preloaded SGPRs. However I think looking for the argument copies here is the wrong approach. The original intrinsic calls should have been annotated with the align return value attribute. Currently this is a burden on the frontend/library call emitting the intrinsic. We could either annotate the intrinsic calls in one of the later passes (maybe AMDGPUCodeGenPrepare), or add a minimum alignment to the intrinsic definition which will always be applied, similar to how intrinsic declarations already get their other attributes
> > do we have that attribute available? could you elaborate in detail?
> OK, I found that.
In another review [[ https://reviews.llvm.org/D80422 | D80422 ]], relevant intrinsics are being annotated with assumed alignment on the return pointer. Unfortunately, in SelectionDAG, we won't have the facility to keep tracking of that hint. I will enhance `AMDGPUCodeGenPrepare` pass to do that similar thing.


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  https://reviews.llvm.org/D80364/new/

https://reviews.llvm.org/D80364