[PATCH] D72175: AMDGPU: Define mode register

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D72175#2051296 <https://reviews.llvm.org/D72175#2051296>, @rampitec wrote:

> In D72175#2050379 <https://reviews.llvm.org/D72175#2050379>, @arsenm wrote:
>
> > Unlike HSAIL, in LLVM the FP mode is going to be a middle end, IR problem. The backend won't be responsible for inserting or maintaining mode switches. All of that should be done in the IR on the constrained FP intrinsics. Separately tracking the bits on the machine level is going to increase the cost and complexity too much (just the one I think is too much, but manageable)
>
>
> Well, actually it was in the SC, so backend. The point to split it is to be able to reschedule without false dependencies and to minimize required switches. At the very least we need to minimize switches.


Minimizing the switches is an IR problem. The backends isn’t going to be responsible for scheduling instructions around mode switches, and we just need to express the possible dependency. You can handle those issues in an IR pass that understands setreg intrinsic calls and constrained intrinsics. The other issue with breaking this down is the documentation for which instructions read which sub fields is quite poor and varies per subtarget (at least for the denormal mode). We would also have to understand the mode switch perfectly, which won’t always be the case if a variable setting is used with s_setreg. In the immediate case we would have to define a lot of variants of setreg setting different mode bit sets


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