[PATCH] D72175: AMDGPU: Define mode register

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.
Herald added a subscriber: kerbowa.

In D72175#1803565 <https://reviews.llvm.org/D72175#1803565>, @rampitec wrote:

> In D72175#1803554 <https://reviews.llvm.org/D72175#1803554>, @arsenm wrote:
>
> > In D72175#1803537 <https://reviews.llvm.org/D72175#1803537>, @rampitec wrote:
> >
> > > I would define individual fields as separate registers. That way we will be able to reschedule instructions across some mode changes if these instructions are not affected by a particular change.
> >
> >
> > I think that's way overcomplicated, especially for the frequency of mode writes. There's a cost to adding each register and register operand
>
>
> We used to have this optimization with HSAIL and it deemed to be quite profitable.


Unlike HSAIL, in LLVM the FP mode is going to be a middle end, IR problem. The backend won't be responsible for inserting or maintaining mode switches. All of that should be done in the IR on the constrained FP intrinsics. Separately tracking the bits on the machine level is going to increase the cost and complexity too much (just the one I think is too much, but manageable)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72175/new/

https://reviews.llvm.org/D72175