[PATCH] D80194: [AMDGPU] Allow PAL to put RO global in .text or .rodata

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, arsenm.
Herald added a project: LLVM.
tpr added a reviewer: kzhuravl.
tpr added a reviewer: nhaehnle.

In LLPC (PAL OS type), I would like to be able to choose whether an RO
constant goes in .text with a relative fixup to reference it (for full
pipeline compilation) or in .rodata with a reloc to reference it (shader
compilation).

This commit allows that. LLPC will override the global's section name
with ".text" to get the global into .text.

Change-Id: I14c9525225572a16f0c01d394565e6ebfa39456d


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80194

Files:
  llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/test/CodeGen/AMDGPU/elf.rodata.ll


Index: llvm/test/CodeGen/AMDGPU/elf.rodata.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/elf.rodata.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=amdgcn -mcpu=fiji -filetype=obj | llvm-readobj --symbols -S --sd - | FileCheck %s
+
+; CHECK: Section {
+; CHECK: Name: .text
+; CHECK: Type: SHT_PROGBITS (0x1)
+; CHECK: Flags [ (0x6)
+; CHECK: Size: 16
+; CHECK: SectionData (
+; CHECK: 0000: 414D4431 414D4431 414D4431 414D4431  |AMD1AMD1AMD1AMD1|
+; CHECK: )
+; CHECK: }
+
+; CHECK: Section {
+; CHECK: Name: .rodata
+; CHECK: Type: SHT_PROGBITS (0x1)
+; CHECK: Flags [ (0x2)
+; CHECK: Size: 16
+; CHECK: SectionData (
+; CHECK: 0000: 414D4432 414D4432 414D4432 414D4432  |AMD2AMD2AMD2AMD2|
+; CHECK: )
+; CHECK: }
+
+
+ at rodata_info_var_1 = internal global [4 x i32][i32 826559809, i32 826559809, i32 826559809, i32 826559809], section ".text"
+ at rodata_info_var_2 = constant [4 x i32][i32 843337025, i32 843337025, i32 843337025, i32 843337025]
Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -568,7 +568,7 @@
 }
 
 bool shouldEmitConstantsToTextSection(const Triple &TT) {
-  return TT.getOS() == Triple::AMDPAL || TT.getArch() == Triple::r600;
+  return TT.getArch() == Triple::r600;
 }
 
 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4648,7 +4648,8 @@
   const Triple &TT = getTargetMachine().getTargetTriple();
   return (GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
           GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
-         AMDGPU::shouldEmitConstantsToTextSection(TT);
+         (AMDGPU::shouldEmitConstantsToTextSection(TT) ||
+          GV->getSection().startswith(".text"));
 }
 
 bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
Index: llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
@@ -35,6 +35,8 @@
   StringRef SectionName = GO->getSection();
   if (SectionName.startswith(".AMDGPU.comment."))
     SK = SectionKind::getMetadata();
+  else if (SectionName.startswith(".text"))
+    SK = SectionKind::getText();
 
   return TargetLoweringObjectFileELF::getExplicitSectionGlobal(GO, SK, TM);
 }


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