[PATCH] D80131: [x86] favor vector constant load to avoid GPR to XMM transfer, part 2

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, RKSimon.
Herald added subscribers: hiraditya, mcrosier.
Herald added a project: LLVM.
spatel retitled this revision from "[x86] favor vector constant load to avoid GPR to XMM transert, part 2" to "[x86] favor vector constant load to avoid GPR to XMM transfer, part 2".

This replaces the build_vector lowering code that was just added in D80013 <https://reviews.llvm.org/D80013> and matches the pattern later from the x86-specific "vzext_movl". That seems to result in the same or better improvements and gets rid of the 'TODO' items from that patch.

AFAICT, we always shrink wider constant vectors to 128-bit on these patterns, so we still get the implicit zero-extension to ymm/zmm without wasting space on larger vector constants. There's a trade-off there because that means we miss potential load-folding.

Similarly, we could load scalar constants here with implicit zero-extension even to 128-bit. That saves constant space, but it means we forego load-folding, and so it increases register pressure. This seems like a good middle-ground between those 2 options?


https://reviews.llvm.org/D80131

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/avx-load-store.ll
  llvm/test/CodeGen/X86/avx2-arith.ll
  llvm/test/CodeGen/X86/combine-udiv.ll
  llvm/test/CodeGen/X86/fcmp-constant.ll
  llvm/test/CodeGen/X86/insert-into-constant-vector.ll
  llvm/test/CodeGen/X86/packss.ll
  llvm/test/CodeGen/X86/pshufb-mask-comments.ll
  llvm/test/CodeGen/X86/ret-mmx.ll
  llvm/test/CodeGen/X86/sad.ll
  llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/X86/vec_set-A.ll
  llvm/test/CodeGen/X86/vec_shift2.ll
  llvm/test/CodeGen/X86/vector-lzcnt-128.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
  llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
  llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
  llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
  llvm/test/CodeGen/X86/vector-shuffle-v1.ll
  llvm/test/CodeGen/X86/vector-tzcnt-128.ll

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