[llvm] 57c3fe7 - [x86] favor vector constant load to avoid GPR to XMM transfer
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sun May 17 08:57:30 PDT 2020
Author: Sanjay Patel
Date: 2020-05-17T11:56:26-04:00
New Revision: 57c3fe76a31663526c78ed6ac3bbb34858c823d2
URL: https://github.com/llvm/llvm-project/commit/57c3fe76a31663526c78ed6ac3bbb34858c823d2
DIFF: https://github.com/llvm/llvm-project/commit/57c3fe76a31663526c78ed6ac3bbb34858c823d2.diff
LOG: [x86] favor vector constant load to avoid GPR to XMM transfer
This build vector lowering pattern came up in D79886.
I've tried to limit the improvement to cases where it looks
clearly better to load, but we could remove the 'TODO'
predicates already if we are willing to overlook some
corner cases.
Differential Revision: https://reviews.llvm.org/D80013
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/combine-udiv.ll
llvm/test/CodeGen/X86/packss.ll
llvm/test/CodeGen/X86/pshufb-mask-comments.ll
llvm/test/CodeGen/X86/ret-mmx.ll
llvm/test/CodeGen/X86/sad.ll
llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
llvm/test/CodeGen/X86/vec_set-A.ll
llvm/test/CodeGen/X86/vec_shift2.ll
llvm/test/CodeGen/X86/vector-lzcnt-128.ll
llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
llvm/test/CodeGen/X86/vector-tzcnt-128.ll
llvm/test/CodeGen/X86/vmovq.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6f0bc73d6a38..655147076a40 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -10192,6 +10192,15 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
if (NumZero == 0)
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
+ // Just load a vector integer constant. Loading is better for code size,
+ // avoids move GPR immediate --> XMM, and reduces register pressure.
+ if (IsAllConstants && VT.isInteger()) {
+ // TODO: Remove -1 restriction with demanded elements improvement?
+ // TODO: Insert 128-bit load into wider undef vector?
+ if (VT.is128BitVector() && !isAllOnesConstant(Item))
+ return SDValue();
+ }
+
if (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
(EltVT == MVT::i64 && Subtarget.is64Bit())) {
assert((VT.is128BitVector() || VT.is256BitVector() ||
diff --git a/llvm/test/CodeGen/X86/combine-udiv.ll b/llvm/test/CodeGen/X86/combine-udiv.ll
index 286ef85195a6..c06719b91e27 100644
--- a/llvm/test/CodeGen/X86/combine-udiv.ll
+++ b/llvm/test/CodeGen/X86/combine-udiv.ll
@@ -498,26 +498,23 @@ define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
; SSE2-LABEL: combine_vec_udiv_nonuniform:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65535,65535,0,65535,65535,65535,65535]
-; SSE2-NEXT: movdqa %xmm0, %xmm1
-; SSE2-NEXT: pand %xmm2, %xmm1
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,0,65535,65535,65535,65535]
+; SSE2-NEXT: movdqa %xmm0, %xmm2
+; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psrlw $3, %xmm3
-; SSE2-NEXT: pandn %xmm3, %xmm2
-; SSE2-NEXT: por %xmm1, %xmm2
-; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm2
-; SSE2-NEXT: psubw %xmm2, %xmm0
-; SSE2-NEXT: movl $32768, %eax # imm = 0x8000
-; SSE2-NEXT: movd %eax, %xmm1
-; SSE2-NEXT: pmulhuw %xmm0, %xmm1
-; SSE2-NEXT: paddw %xmm2, %xmm1
-; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,65535,65535,0,0,65535,65535,0]
-; SSE2-NEXT: movdqa %xmm0, %xmm2
-; SSE2-NEXT: pandn %xmm1, %xmm2
-; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
-; SSE2-NEXT: pand %xmm0, %xmm1
+; SSE2-NEXT: pandn %xmm3, %xmm1
; SSE2-NEXT: por %xmm2, %xmm1
-; SSE2-NEXT: movdqa %xmm1, %xmm0
+; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm1
+; SSE2-NEXT: psubw %xmm1, %xmm0
+; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: paddw %xmm1, %xmm0
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,0,0,65535,65535,0]
+; SSE2-NEXT: movdqa %xmm1, %xmm2
+; SSE2-NEXT: pandn %xmm0, %xmm2
+; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pand %xmm1, %xmm0
+; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE41-LABEL: combine_vec_udiv_nonuniform:
@@ -527,13 +524,11 @@ define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE41-NEXT: psubw %xmm1, %xmm0
-; SSE41-NEXT: movl $32768, %eax # imm = 0x8000
-; SSE41-NEXT: movd %eax, %xmm2
-; SSE41-NEXT: pmulhuw %xmm0, %xmm2
-; SSE41-NEXT: paddw %xmm1, %xmm2
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = <4096,2048,8,u,u,2,2,u>
-; SSE41-NEXT: pmulhuw %xmm2, %xmm0
-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[3,4],xmm0[5,6],xmm2[7]
+; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: paddw %xmm1, %xmm0
+; SSE41-NEXT: movdqa {{.*#+}} xmm1 = <4096,2048,8,u,u,2,2,u>
+; SSE41-NEXT: pmulhuw %xmm0, %xmm1
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4],xmm1[5,6],xmm0[7]
; SSE41-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_nonuniform:
@@ -542,9 +537,7 @@ define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: movl $32768, %eax # imm = 0x8000
-; AVX-NEXT: vmovd %eax, %xmm2
-; AVX-NEXT: vpmulhuw %xmm2, %xmm0, %xmm0
+; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4],xmm1[5,6],xmm0[7]
@@ -555,9 +548,7 @@ define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm1
; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
-; XOP-NEXT: movl $32768, %eax # imm = 0x8000
-; XOP-NEXT: vmovd %eax, %xmm2
-; XOP-NEXT: vpmulhuw %xmm2, %xmm0, %xmm0
+; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
@@ -649,14 +640,12 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; SSE2-NEXT: pand %xmm2, %xmm1
; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
-; SSE2-NEXT: movl $171, %eax
-; SSE2-NEXT: movd %eax, %xmm3
-; SSE2-NEXT: pmullw %xmm0, %xmm3
-; SSE2-NEXT: psrlw $8, %xmm3
-; SSE2-NEXT: packuswb %xmm3, %xmm3
-; SSE2-NEXT: psrlw $7, %xmm3
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm3
-; SSE2-NEXT: pandn %xmm3, %xmm2
+; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0
+; SSE2-NEXT: psrlw $8, %xmm0
+; SSE2-NEXT: packuswb %xmm0, %xmm0
+; SSE2-NEXT: psrlw $7, %xmm0
+; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
@@ -664,10 +653,8 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; SSE41-LABEL: combine_vec_udiv_nonuniform4:
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1
-; SSE41-NEXT: movl $171, %eax
-; SSE41-NEXT: movd %eax, %xmm0
-; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
-; SSE41-NEXT: pmullw %xmm0, %xmm2
+; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm2
; SSE41-NEXT: psrlw $8, %xmm2
; SSE41-NEXT: packuswb %xmm2, %xmm2
; SSE41-NEXT: psrlw $7, %xmm2
@@ -677,26 +664,36 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq
;
-; AVX-LABEL: combine_vec_udiv_nonuniform4:
-; AVX: # %bb.0:
-; AVX-NEXT: movl $171, %eax
-; AVX-NEXT: vmovd %eax, %xmm1
-; AVX-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX-NEXT: vpmullw %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vpsrlw $8, %xmm1, %xmm1
-; AVX-NEXT: vpackuswb %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vpsrlw $7, %xmm1, %xmm1
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
-; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
-; AVX-NEXT: retq
+; AVX1-LABEL: combine_vec_udiv_nonuniform4:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
+; AVX1-NEXT: vpackuswb %xmm1, %xmm1, %xmm1
+; AVX1-NEXT: vpsrlw $7, %xmm1, %xmm1
+; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; AVX1-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: combine_vec_udiv_nonuniform4:
+; AVX2: # %bb.0:
+; AVX2-NEXT: movl $171, %eax
+; AVX2-NEXT: vmovd %eax, %xmm1
+; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX2-NEXT: vpmullw %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vpsrlw $8, %xmm1, %xmm1
+; AVX2-NEXT: vpackuswb %xmm1, %xmm1, %xmm1
+; AVX2-NEXT: vpsrlw $7, %xmm1, %xmm1
+; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; AVX2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: retq
;
; XOP-LABEL: combine_vec_udiv_nonuniform4:
; XOP: # %bb.0:
-; XOP-NEXT: movl $171, %eax
-; XOP-NEXT: vmovd %eax, %xmm1
-; XOP-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; XOP-NEXT: vpmullw %xmm1, %xmm2, %xmm1
+; XOP-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; XOP-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOP-NEXT: vpperm {{.*#+}} xmm1 = xmm1[1,3,5,7,9,11,13,15],xmm2[1,3,5,7,9,11,13,15]
; XOP-NEXT: movl $249, %eax
diff --git a/llvm/test/CodeGen/X86/packss.ll b/llvm/test/CodeGen/X86/packss.ll
index 4eed19a4fab9..9c8d1f301f62 100644
--- a/llvm/test/CodeGen/X86/packss.ll
+++ b/llvm/test/CodeGen/X86/packss.ll
@@ -158,14 +158,14 @@ define <8 x i16> @trunc_ashr_v4i64_demandedelts(<4 x i64> %a0) {
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psllq $63, %xmm1
; X86-SSE-NEXT: psllq $63, %xmm0
-; X86-SSE-NEXT: movl $1, %eax
-; X86-SSE-NEXT: movd %eax, %xmm2
; X86-SSE-NEXT: psrlq $63, %xmm0
+; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = <1,0,u,u>
; X86-SSE-NEXT: pxor %xmm2, %xmm0
-; X86-SSE-NEXT: psubq %xmm2, %xmm0
+; X86-SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; X86-SSE-NEXT: paddq %xmm3, %xmm0
; X86-SSE-NEXT: psrlq $63, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm1
-; X86-SSE-NEXT: psubq %xmm2, %xmm1
+; X86-SSE-NEXT: paddq %xmm3, %xmm1
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; X86-SSE-NEXT: packssdw %xmm1, %xmm0
diff --git a/llvm/test/CodeGen/X86/pshufb-mask-comments.ll b/llvm/test/CodeGen/X86/pshufb-mask-comments.ll
index 72cac5bdc83e..9a1a000db93c 100644
--- a/llvm/test/CodeGen/X86/pshufb-mask-comments.ll
+++ b/llvm/test/CodeGen/X86/pshufb-mask-comments.ll
@@ -54,9 +54,8 @@ define <16 x i8> @test4(<16 x i8> %V, <2 x i64>* %P) {
define <16 x i8> @test5(<16 x i8> %V) {
; CHECK-LABEL: test5:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: movd %eax, %xmm1
-; CHECK-NEXT: movdqa %xmm1, (%rax)
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1,0]
+; CHECK-NEXT: movaps %xmm1, (%rax)
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1,1]
; CHECK-NEXT: movaps %xmm1, (%rax)
; CHECK-NEXT: pshufb (%rax), %xmm0
diff --git a/llvm/test/CodeGen/X86/ret-mmx.ll b/llvm/test/CodeGen/X86/ret-mmx.ll
index 3797b6db4c1a..bca47e182953 100644
--- a/llvm/test/CodeGen/X86/ret-mmx.ll
+++ b/llvm/test/CodeGen/X86/ret-mmx.ll
@@ -32,8 +32,7 @@ define <1 x i64> @t2() nounwind {
define <2 x i32> @t3() nounwind {
; CHECK-LABEL: t3:
; CHECK: ## %bb.0:
-; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: movd %eax, %xmm0
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = <1,0,u,u>
; CHECK-NEXT: retq
ret <2 x i32> <i32 1, i32 0>
}
@@ -41,8 +40,7 @@ define <2 x i32> @t3() nounwind {
define double @t4() nounwind {
; CHECK-LABEL: t4:
; CHECK: ## %bb.0:
-; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: movd %eax, %xmm0
+; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: retq
ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
}
diff --git a/llvm/test/CodeGen/X86/sad.ll b/llvm/test/CodeGen/X86/sad.ll
index 5f0f225a4494..66a8661698a5 100644
--- a/llvm/test/CodeGen/X86/sad.ll
+++ b/llvm/test/CodeGen/X86/sad.ll
@@ -986,33 +986,63 @@ define i32 @sad_unroll_nonzero_initial(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x
; SSE2-NEXT: movdqu (%rdx), %xmm0
; SSE2-NEXT: movdqu (%rcx), %xmm2
; SSE2-NEXT: psadbw %xmm0, %xmm2
-; SSE2-NEXT: movl $1, %eax
-; SSE2-NEXT: movd %eax, %xmm0
+; SSE2-NEXT: paddd %xmm1, %xmm2
+; SSE2-NEXT: paddd {{.*}}(%rip), %xmm2
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1]
; SSE2-NEXT: paddd %xmm2, %xmm0
-; SSE2-NEXT: paddd %xmm1, %xmm0
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
; SSE2-NEXT: paddd %xmm0, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
-; SSE2-NEXT: paddd %xmm1, %xmm0
-; SSE2-NEXT: movd %xmm0, %eax
+; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq
;
-; AVX-LABEL: sad_unroll_nonzero_initial:
-; AVX: # %bb.0: # %bb
-; AVX-NEXT: vmovdqu (%rdi), %xmm0
-; AVX-NEXT: vpsadbw (%rsi), %xmm0, %xmm0
-; AVX-NEXT: vmovdqu (%rdx), %xmm1
-; AVX-NEXT: vpsadbw (%rcx), %xmm1, %xmm1
-; AVX-NEXT: movl $1, %eax
-; AVX-NEXT: vmovd %eax, %xmm2
-; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1
-; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
-; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
-; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vmovd %xmm0, %eax
-; AVX-NEXT: retq
+; AVX1-LABEL: sad_unroll_nonzero_initial:
+; AVX1: # %bb.0: # %bb
+; AVX1-NEXT: vmovdqu (%rdi), %xmm0
+; AVX1-NEXT: vpsadbw (%rsi), %xmm0, %xmm0
+; AVX1-NEXT: vmovdqu (%rdx), %xmm1
+; AVX1-NEXT: vpsadbw (%rcx), %xmm1, %xmm1
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vmovd %xmm0, %eax
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: sad_unroll_nonzero_initial:
+; AVX2: # %bb.0: # %bb
+; AVX2-NEXT: vmovdqu (%rdi), %xmm0
+; AVX2-NEXT: vpsadbw (%rsi), %xmm0, %xmm0
+; AVX2-NEXT: vmovdqu (%rdx), %xmm1
+; AVX2-NEXT: vpsadbw (%rcx), %xmm1, %xmm1
+; AVX2-NEXT: movl $1, %eax
+; AVX2-NEXT: vmovd %eax, %xmm2
+; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1
+; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
+; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vmovd %xmm0, %eax
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: sad_unroll_nonzero_initial:
+; AVX512: # %bb.0: # %bb
+; AVX512-NEXT: vmovdqu (%rdi), %xmm0
+; AVX512-NEXT: vpsadbw (%rsi), %xmm0, %xmm0
+; AVX512-NEXT: vmovdqu (%rdx), %xmm1
+; AVX512-NEXT: vpsadbw (%rcx), %xmm1, %xmm1
+; AVX512-NEXT: movl $1, %eax
+; AVX512-NEXT: vmovd %eax, %xmm2
+; AVX512-NEXT: vpaddd %xmm2, %xmm1, %xmm1
+; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
+; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vmovd %xmm0, %eax
+; AVX512-NEXT: retq
bb:
%tmp = load <16 x i8>, <16 x i8>* %arg, align 1
%tmp4 = load <16 x i8>, <16 x i8>* %arg1, align 1
diff --git a/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll b/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
index b23921963d67..1eee782f90ca 100644
--- a/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
+++ b/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
@@ -323,13 +323,12 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
;
; CHECK-SSE41-LABEL: test_srem_even_allones_eq:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-SSE41-NEXT: movd %eax, %xmm1
-; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm1
-; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm2
-; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
+; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = <2454267027,u,0,u>
+; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm2
+; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,1,4294967295,1]
; CHECK-SSE41-NEXT: pmulld %xmm0, %xmm1
; CHECK-SSE41-NEXT: paddd %xmm2, %xmm1
@@ -348,13 +347,11 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_even_allones_eq:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-AVX1-NEXT: vmovd %eax, %xmm1
-; CHECK-AVX1-NEXT: vpmuldq %xmm1, %xmm0, %xmm1
-; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuldq {{.*}}(%rip), %xmm2, %xmm2
-; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
+; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; CHECK-AVX1-NEXT: vpmuldq {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuldq {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2
; CHECK-AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsrad $3, %xmm1, %xmm2
@@ -374,9 +371,7 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027]
; CHECK-AVX2-NEXT: vpmuldq %xmm2, %xmm1, %xmm1
-; CHECK-AVX2-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-AVX2-NEXT: vmovd %eax, %xmm2
-; CHECK-AVX2-NEXT: vpmuldq %xmm2, %xmm0, %xmm2
+; CHECK-AVX2-NEXT: vpmuldq {{.*}}(%rip), %xmm0, %xmm2
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2
@@ -455,13 +450,12 @@ define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
;
; CHECK-SSE41-LABEL: test_srem_even_allones_ne:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-SSE41-NEXT: movd %eax, %xmm1
-; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm1
-; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm2
-; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
+; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = <2454267027,u,0,u>
+; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm2
+; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,1,4294967295,1]
; CHECK-SSE41-NEXT: pmulld %xmm0, %xmm1
; CHECK-SSE41-NEXT: paddd %xmm2, %xmm1
@@ -480,13 +474,11 @@ define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_even_allones_ne:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-AVX1-NEXT: vmovd %eax, %xmm1
-; CHECK-AVX1-NEXT: vpmuldq %xmm1, %xmm0, %xmm1
-; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuldq {{.*}}(%rip), %xmm2, %xmm2
-; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
+; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; CHECK-AVX1-NEXT: vpmuldq {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuldq {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2
; CHECK-AVX1-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsrad $3, %xmm1, %xmm2
@@ -506,9 +498,7 @@ define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027]
; CHECK-AVX2-NEXT: vpmuldq %xmm2, %xmm1, %xmm1
-; CHECK-AVX2-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-AVX2-NEXT: vmovd %eax, %xmm2
-; CHECK-AVX2-NEXT: vpmuldq %xmm2, %xmm0, %xmm2
+; CHECK-AVX2-NEXT: vpmuldq {{.*}}(%rip), %xmm0, %xmm2
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2
@@ -1322,13 +1312,12 @@ define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
;
; CHECK-SSE41-LABEL: test_srem_even_one:
; CHECK-SSE41: # %bb.0:
-; CHECK-SSE41-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-SSE41-NEXT: movd %eax, %xmm1
-; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm1
-; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm2
-; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
+; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = <2454267027,u,0,u>
+; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm2
+; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: paddd %xmm0, %xmm2
; CHECK-SSE41-NEXT: movdqa %xmm2, %xmm1
; CHECK-SSE41-NEXT: psrad $3, %xmm1
@@ -1345,13 +1334,11 @@ define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
;
; CHECK-AVX1-LABEL: test_srem_even_one:
; CHECK-AVX1: # %bb.0:
-; CHECK-AVX1-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-AVX1-NEXT: vmovd %eax, %xmm1
-; CHECK-AVX1-NEXT: vpmuldq %xmm1, %xmm0, %xmm1
-; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
-; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
-; CHECK-AVX1-NEXT: vpmuldq {{.*}}(%rip), %xmm2, %xmm2
-; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
+; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; CHECK-AVX1-NEXT: vpmuldq {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpmuldq {{.*}}(%rip), %xmm0, %xmm2
+; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpaddd %xmm0, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsrad $3, %xmm1, %xmm2
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5],xmm2[6,7]
@@ -1370,9 +1357,7 @@ define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027]
; CHECK-AVX2-NEXT: vpmuldq %xmm2, %xmm1, %xmm1
-; CHECK-AVX2-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-AVX2-NEXT: vmovd %eax, %xmm2
-; CHECK-AVX2-NEXT: vpmuldq %xmm2, %xmm0, %xmm2
+; CHECK-AVX2-NEXT: vpmuldq {{.*}}(%rip), %xmm0, %xmm2
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
; CHECK-AVX2-NEXT: vpaddd %xmm0, %xmm1, %xmm1
diff --git a/llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll b/llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
index 089acd843f38..b83dcb6a0cd8 100644
--- a/llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
+++ b/llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
@@ -1002,10 +1002,8 @@ define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
-; CHECK-SSE2-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-SSE2-NEXT: movd %eax, %xmm2
-; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
-; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
+; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
@@ -1031,10 +1029,8 @@ define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
-; CHECK-SSE41-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-SSE41-NEXT: movd %eax, %xmm3
-; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm3
-; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,3,3]
+; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm1
+; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-SSE41-NEXT: psrld $2, %xmm2
@@ -1050,9 +1046,7 @@ define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
-; CHECK-AVX1-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-AVX1-NEXT: vmovd %eax, %xmm3
-; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm2, %xmm2
+; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
@@ -1072,9 +1066,7 @@ define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2454267027,2454267027,2454267027,2454267027]
; CHECK-AVX2-NEXT: vpmuludq %xmm3, %xmm2, %xmm2
-; CHECK-AVX2-NEXT: movl $-1840700269, %eax # imm = 0x92492493
-; CHECK-AVX2-NEXT: vmovd %eax, %xmm3
-; CHECK-AVX2-NEXT: vpmuludq %xmm3, %xmm1, %xmm1
+; CHECK-AVX2-NEXT: vpmuludq {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
; CHECK-AVX2-NEXT: vpsrld $2, %xmm1, %xmm1
@@ -2635,14 +2627,12 @@ define <4 x i32> @test_urem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) no
;
; CHECK-AVX2-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
; CHECK-AVX2: # %bb.0:
-; CHECK-AVX2-NEXT: movl $1, %eax
-; CHECK-AVX2-NEXT: vmovd %eax, %xmm1
-; CHECK-AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm1
+; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [2454267027,2147483649,268435456,0]
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [2454267027,2147483649,268435456,0]
+; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm3
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
-; CHECK-AVX2-NEXT: vpmuludq %xmm4, %xmm2, %xmm2
-; CHECK-AVX2-NEXT: vpmuludq %xmm3, %xmm1, %xmm1
+; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm4, %xmm2
+; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1
diff --git a/llvm/test/CodeGen/X86/vec_set-A.ll b/llvm/test/CodeGen/X86/vec_set-A.ll
index 0a8b4d8a4407..e246ef047231 100644
--- a/llvm/test/CodeGen/X86/vec_set-A.ll
+++ b/llvm/test/CodeGen/X86/vec_set-A.ll
@@ -5,14 +5,12 @@
define <2 x i64> @test1() nounwind {
; X86-LABEL: test1:
; X86: # %bb.0:
-; X86-NEXT: movl $1, %eax
-; X86-NEXT: movd %eax, %xmm0
+; X86-NEXT: movaps {{.*#+}} xmm0 = [1,0,0,0]
; X86-NEXT: retl
;
; X64-LABEL: test1:
; X64: # %bb.0:
-; X64-NEXT: movl $1, %eax
-; X64-NEXT: movd %eax, %xmm0
+; X64-NEXT: movaps {{.*#+}} xmm0 = [1,0]
; X64-NEXT: retq
ret <2 x i64> < i64 1, i64 0 >
}
diff --git a/llvm/test/CodeGen/X86/vec_shift2.ll b/llvm/test/CodeGen/X86/vec_shift2.ll
index a38187f190f9..1f386bb5a1da 100644
--- a/llvm/test/CodeGen/X86/vec_shift2.ll
+++ b/llvm/test/CodeGen/X86/vec_shift2.ll
@@ -5,12 +5,12 @@
define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind {
; X32-LABEL: t1:
; X32: # %bb.0:
-; X32-NEXT: psrlw $14, %xmm0
+; X32-NEXT: psrlw {{\.LCPI.*}}, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: t1:
; X64: # %bb.0:
-; X64-NEXT: psrlw $14, %xmm0
+; X64-NEXT: psrlw {{.*}}(%rip), %xmm0
; X64-NEXT: retq
%tmp1 = bitcast <2 x i64> %b1 to <8 x i16>
%tmp2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp1, <8 x i16> bitcast (<4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > to <8 x i16>) ) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-128.ll b/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
index 95b1ec0fee6b..ea77de539337 100644
--- a/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
@@ -1666,26 +1666,22 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
define <2 x i64> @foldv2i64() nounwind {
; SSE-LABEL: foldv2i64:
; SSE: # %bb.0:
-; SSE-NEXT: movl $55, %eax
-; SSE-NEXT: movd %eax, %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0]
; SSE-NEXT: retq
;
; NOBW-LABEL: foldv2i64:
; NOBW: # %bb.0:
-; NOBW-NEXT: movl $55, %eax
-; NOBW-NEXT: vmovd %eax, %xmm0
+; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0]
; NOBW-NEXT: retq
;
; AVX512VLBWDQ-LABEL: foldv2i64:
; AVX512VLBWDQ: # %bb.0:
-; AVX512VLBWDQ-NEXT: movl $55, %eax
-; AVX512VLBWDQ-NEXT: vmovd %eax, %xmm0
+; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0]
; AVX512VLBWDQ-NEXT: retq
;
; X32-SSE-LABEL: foldv2i64:
; X32-SSE: # %bb.0:
-; X32-SSE-NEXT: movl $55, %eax
-; X32-SSE-NEXT: movd %eax, %xmm0
+; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0,0,0]
; X32-SSE-NEXT: retl
%out = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> <i64 256, i64 -1>, i1 0)
ret <2 x i64> %out
@@ -1694,26 +1690,22 @@ define <2 x i64> @foldv2i64() nounwind {
define <2 x i64> @foldv2i64u() nounwind {
; SSE-LABEL: foldv2i64u:
; SSE: # %bb.0:
-; SSE-NEXT: movl $55, %eax
-; SSE-NEXT: movd %eax, %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0]
; SSE-NEXT: retq
;
; NOBW-LABEL: foldv2i64u:
; NOBW: # %bb.0:
-; NOBW-NEXT: movl $55, %eax
-; NOBW-NEXT: vmovd %eax, %xmm0
+; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0]
; NOBW-NEXT: retq
;
; AVX512VLBWDQ-LABEL: foldv2i64u:
; AVX512VLBWDQ: # %bb.0:
-; AVX512VLBWDQ-NEXT: movl $55, %eax
-; AVX512VLBWDQ-NEXT: vmovd %eax, %xmm0
+; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0]
; AVX512VLBWDQ-NEXT: retq
;
; X32-SSE-LABEL: foldv2i64u:
; X32-SSE: # %bb.0:
-; X32-SSE-NEXT: movl $55, %eax
-; X32-SSE-NEXT: movd %eax, %xmm0
+; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0,0,0]
; X32-SSE-NEXT: retl
%out = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> <i64 256, i64 -1>, i1 -1)
ret <2 x i64> %out
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
index 5b740277a2e9..0807aa6dab09 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
@@ -740,12 +740,10 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00(<32 x i8> %a, <32 x i8> %b) {
; AVX1-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX1: # %bb.0:
-; AVX1-NEXT: movl $15, %eax
-; AVX1-NEXT: vmovd %eax, %xmm1
+; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm1
-; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
@@ -774,12 +772,10 @@ define <32 x i8> @shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
;
; XOPAVX1-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; XOPAVX1: # %bb.0:
-; XOPAVX1-NEXT: movl $15, %eax
-; XOPAVX1-NEXT: vmovd %eax, %xmm1
+; XOPAVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; XOPAVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm1
-; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; XOPAVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
-; XOPAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; XOPAVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: shuffle_v32i8_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
@@ -1627,13 +1623,11 @@ define <32 x i8> @shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
;
; XOPAVX1-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; XOPAVX1: # %bb.0:
-; XOPAVX1-NEXT: movl $31, %eax
-; XOPAVX1-NEXT: vmovd %eax, %xmm1
+; XOPAVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; XOPAVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm1
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; XOPAVX1-NEXT: vpperm %xmm1, %xmm2, %xmm0, %xmm1
-; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; XOPAVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
-; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; XOPAVX1-NEXT: vpperm {{.*#+}} xmm0 = xmm2[15],xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; XOPAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
@@ -2143,33 +2137,25 @@ define <32 x i8> @shuffle_v32i8_00_14_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
define <32 x i8> @shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00(<32 x i8> %a, <32 x i8> %b) {
; AVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX1: # %bb.0:
-; AVX1-NEXT: movl $15, %eax
-; AVX1-NEXT: vmovd %eax, %xmm1
-; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX2: # %bb.0:
-; AVX2-NEXT: movl $15, %eax
-; AVX2-NEXT: vmovd %eax, %xmm1
-; AVX2-NEXT: vpshufb %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,0,1]
; AVX2-NEXT: retq
;
; AVX512VLBW-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX512VLBW: # %bb.0:
-; AVX512VLBW-NEXT: movl $15, %eax
-; AVX512VLBW-NEXT: vmovd %eax, %xmm1
-; AVX512VLBW-NEXT: vpshufb %xmm1, %xmm0, %xmm0
+; AVX512VLBW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
; AVX512VLBW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,0,1]
; AVX512VLBW-NEXT: retq
;
; AVX512VLVBMI-SLOW-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX512VLVBMI-SLOW: # %bb.0:
-; AVX512VLVBMI-SLOW-NEXT: movl $15, %eax
-; AVX512VLVBMI-SLOW-NEXT: vmovd %eax, %xmm1
-; AVX512VLVBMI-SLOW-NEXT: vpshufb %xmm1, %xmm0, %xmm0
+; AVX512VLVBMI-SLOW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
; AVX512VLVBMI-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,0,1]
; AVX512VLVBMI-SLOW-NEXT: retq
;
@@ -2182,17 +2168,13 @@ define <32 x i8> @shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
;
; XOPAVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; XOPAVX1: # %bb.0:
-; XOPAVX1-NEXT: movl $15, %eax
-; XOPAVX1-NEXT: vmovd %eax, %xmm1
-; XOPAVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
+; XOPAVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; XOPAVX2: # %bb.0:
-; XOPAVX2-NEXT: movl $15, %eax
-; XOPAVX2-NEXT: vmovd %eax, %xmm1
-; XOPAVX2-NEXT: vpshufb %xmm1, %xmm0, %xmm0
+; XOPAVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
; XOPAVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,0,1]
; XOPAVX2-NEXT: retq
%shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -2808,12 +2790,11 @@ define <32 x i8> @shuffle_v32i8_00_14_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
define <32 x i8> @shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_31_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16(<32 x i8> %a, <32 x i8> %b) {
; AVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_31_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16:
; AVX1: # %bb.0:
-; AVX1-NEXT: movl $15, %eax
-; AVX1-NEXT: vmovd %eax, %xmm1
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm2
-; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
+; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2OR512VL-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_31_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16:
@@ -2823,12 +2804,11 @@ define <32 x i8> @shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
;
; XOPAVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_31_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16:
; XOPAVX1: # %bb.0:
-; XOPAVX1-NEXT: movl $15, %eax
-; XOPAVX1-NEXT: vmovd %eax, %xmm1
-; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; XOPAVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm2
-; XOPAVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
-; XOPAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; XOPAVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; XOPAVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
+; XOPAVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
+; XOPAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; XOPAVX1-NEXT: retq
;
; XOPAVX2-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_31_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16:
@@ -3160,9 +3140,7 @@ define <32 x i8> @shuffle_v32i8_00_14_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
define <32 x i8> @shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16_31(<32 x i8> %a, <32 x i8> %b) {
; AVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16_31:
; AVX1: # %bb.0:
-; AVX1-NEXT: movl $15, %eax
-; AVX1-NEXT: vmovd %eax, %xmm1
-; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,15]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
@@ -3175,9 +3153,7 @@ define <32 x i8> @shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
;
; XOPAVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16_31:
; XOPAVX1: # %bb.0:
-; XOPAVX1-NEXT: movl $15, %eax
-; XOPAVX1-NEXT: vmovd %eax, %xmm1
-; XOPAVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm1
+; XOPAVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; XOPAVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,15]
; XOPAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
index 8fcf2361c0cd..91301f319b02 100644
--- a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
@@ -1576,44 +1576,37 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
define <2 x i64> @foldv2i64() nounwind {
; SSE-LABEL: foldv2i64:
; SSE: # %bb.0:
-; SSE-NEXT: movl $8, %eax
-; SSE-NEXT: movd %eax, %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0]
; SSE-NEXT: retq
;
; AVX-LABEL: foldv2i64:
; AVX: # %bb.0:
-; AVX-NEXT: movl $8, %eax
-; AVX-NEXT: vmovd %eax, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; AVX-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: foldv2i64:
; AVX512VPOPCNTDQ: # %bb.0:
-; AVX512VPOPCNTDQ-NEXT: movl $8, %eax
-; AVX512VPOPCNTDQ-NEXT: vmovd %eax, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: foldv2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
-; AVX512VPOPCNTDQVL-NEXT: movl $8, %eax
-; AVX512VPOPCNTDQVL-NEXT: vmovd %eax, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv2i64:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: movl $8, %eax
-; BITALG_NOVLX-NEXT: vmovd %eax, %xmm0
+; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv2i64:
; BITALG: # %bb.0:
-; BITALG-NEXT: movl $8, %eax
-; BITALG-NEXT: vmovd %eax, %xmm0
+; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; BITALG-NEXT: retq
;
; X32-SSE-LABEL: foldv2i64:
; X32-SSE: # %bb.0:
-; X32-SSE-NEXT: movl $8, %eax
-; X32-SSE-NEXT: movd %eax, %xmm0
+; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,0,0]
; X32-SSE-NEXT: retl
%out = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> <i64 256, i64 -1>, i1 0)
ret <2 x i64> %out
@@ -1622,44 +1615,37 @@ define <2 x i64> @foldv2i64() nounwind {
define <2 x i64> @foldv2i64u() nounwind {
; SSE-LABEL: foldv2i64u:
; SSE: # %bb.0:
-; SSE-NEXT: movl $8, %eax
-; SSE-NEXT: movd %eax, %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0]
; SSE-NEXT: retq
;
; AVX-LABEL: foldv2i64u:
; AVX: # %bb.0:
-; AVX-NEXT: movl $8, %eax
-; AVX-NEXT: vmovd %eax, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; AVX-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: foldv2i64u:
; AVX512VPOPCNTDQ: # %bb.0:
-; AVX512VPOPCNTDQ-NEXT: movl $8, %eax
-; AVX512VPOPCNTDQ-NEXT: vmovd %eax, %xmm0
+; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: foldv2i64u:
; AVX512VPOPCNTDQVL: # %bb.0:
-; AVX512VPOPCNTDQVL-NEXT: movl $8, %eax
-; AVX512VPOPCNTDQVL-NEXT: vmovd %eax, %xmm0
+; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv2i64u:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: movl $8, %eax
-; BITALG_NOVLX-NEXT: vmovd %eax, %xmm0
+; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv2i64u:
; BITALG: # %bb.0:
-; BITALG-NEXT: movl $8, %eax
-; BITALG-NEXT: vmovd %eax, %xmm0
+; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
; BITALG-NEXT: retq
;
; X32-SSE-LABEL: foldv2i64u:
; X32-SSE: # %bb.0:
-; X32-SSE-NEXT: movl $8, %eax
-; X32-SSE-NEXT: movd %eax, %xmm0
+; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,0,0]
; X32-SSE-NEXT: retl
%out = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> <i64 256, i64 -1>, i1 -1)
ret <2 x i64> %out
diff --git a/llvm/test/CodeGen/X86/vmovq.ll b/llvm/test/CodeGen/X86/vmovq.ll
index 2b4ae6795733..3b9a8e2725c9 100644
--- a/llvm/test/CodeGen/X86/vmovq.ll
+++ b/llvm/test/CodeGen/X86/vmovq.ll
@@ -5,20 +5,14 @@
define <2 x i64> @PR25554(<2 x i64> %v0, <2 x i64> %v1) {
; SSE-LABEL: PR25554:
; SSE: # %bb.0:
-; SSE-NEXT: movl $1, %eax
-; SSE-NEXT: movq %rax, %xmm1
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; SSE-NEXT: paddq %xmm1, %xmm0
+; SSE-NEXT: por {{.*}}(%rip), %xmm0
+; SSE-NEXT: paddq {{.*}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: PR25554:
; AVX: # %bb.0:
-; AVX-NEXT: movl $1, %eax
-; AVX-NEXT: vmovq %rax, %xmm1
-; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; AVX-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%c1 = or <2 x i64> %v0, <i64 1, i64 0>
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