[PATCH] D79638: [llvm][SVE] IR intrinscs for matrix multiplication instructions.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:2273
+//
+def int_aarch64_sve_mmla : AdvSIMD_3VectorArg_Intrinsic;
+
----------------
sdesmalen wrote:
> Can you rename this intrinsic to `int_aarch64_sve_fmmla` to match the instruction and make it clear the intrinsic is only valid for FP values?
Yup, thank you for the heads up!


================
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:7603
+
+  def : Pat<(nxv4i32 (op (nxv4i32 ZPR32:$Zda), (nxv16i8 ZPR8:$Zn), (nxv16i8 ZPR8:$Zm))),
+            (!cast<Instruction>(NAME) ZPR32:$Zda, ZPR8:$Zn, ZPR8:$Zm)>;
----------------
sdesmalen wrote:
> Please use `SVE_3_Op_Pat` for these patterns.
Neat, thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79638/new/

https://reviews.llvm.org/D79638