[PATCH] D79776: [AMDGPU] Allow use of StackPtrOffsetReg when building spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll:39
+; CHECK-LABEL: test_limited_sgpr
+define amdgpu_kernel void @test_limited_sgpr(<1280 x i32> addrspace(1)* %out, <1280 x i32> addrspace(1)* %in) #0 {
+entry:
----------------
Needs to check something


================
Comment at: llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll:45
+  %aptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %in, i32 %tid
+  %a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr
+
----------------
A more directed tests would be better. We have a few others relying on splitting up giant vector loads, and they're some  of the slowest tests in the entire lit suite


================
Comment at: llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll:65
 
+attributes #0 = { "amdgpu-num-sgpr"="30" }
 attributes #1 = { nounwind readnone }
----------------
Can you use amdgpu-max-waves-per-eu? I'm trying to move away from the direct register limit attributes


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79776/new/

https://reviews.llvm.org/D79776