[PATCH] D79808: [AMDGPU] Make v4i64/v4f64/v8i64/v8f64 legal

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added a reviewer: arsenm.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

We can produce such vectors in the Promote Alloca pass,
but we are unable to use movrel to operate it and lower
via scratch. Making it legal makes SI_INDIRECT patterns
work.

There is more work to do in subsequent changes:

1. We initialize m0 twice to access each dword. It shall

be possible to only do it once and increment base register
number instead.

2. We also need v16i64/v16f64 but these first need to be

added to tablegen.


https://reviews.llvm.org/D79808

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
  llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
  llvm/test/CodeGen/AMDGPU/idot2.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
  llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
  llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
  llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
  llvm/test/CodeGen/AMDGPU/saddo.ll
  llvm/test/CodeGen/AMDGPU/select.f16.ll
  llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll
  llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll
  llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
  llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D79808.263520.patch
Type: text/x-patch
Size: 141357 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200512/03eca49a/attachment-0001.bin>