[PATCH] D79768: [ARM] Exclude LR from register classes in low overhead loops

Tue May 12 15:05:09 PDT 2020

dmgreen added a comment.

I thought this one might get some pushback. I contemplated starting the summary with "Bear with me..."

But it's not really just stopping LR from spilling between the t2LoopDec and the t2LoopEnd, although that will cause even larger problems that we are seeing.
If a low overhead loop sets LR to anything else inside the loop (calls, spills, etc), then the branch info is cleared and the next time you hit the LE it's like the first time again. Architecturally the loop info is created when you execute an LE and cleared when you otherwise write to LR. So by using LR for anything else you end up loosing all the benefits of a low overhead loop, and there are times where apparently this can be even worse than not using a low overhead loop at all.
So it might deserve a big hammer if it needs one.

But having said that this doesn't entirely solve my problem, and there are still times when we can hit poor register allocation. I think I would also like to change t2DoLoopStart to def GPRlr and use a rGPR reg, more like t2DLS should. That might need quite a bit of changes in the backend pass, from what I've seen, but it seems more "glued together".
Even with that I think there might be times when we end up spilling LR at the wrong place, but it becomes a lot rarer.

> In particular, trying to list out all the possible register classes seems tricky.

Are you worried about more than the 4 + 2 extra that are here? This, with an assert in the NDEBUG block, managed to pass all the benchmarks I threw it at plus all the llvm tests. Do you worry it will need a lot of others?

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https://reviews.llvm.org/D79768