[llvm] 9f0b736 - [AMDGPU] Add AGPRs to getRegClassForSizeOnBank

[Austin Kerbow via llvm-commits]

Author: Austin Kerbow
Date: 2020-05-12T10:14:00-07:00
New Revision: 9f0b736126cb55f194f51c966b0db90aa4cbcd02

URL: https://github.com/llvm/llvm-project/commit/9f0b736126cb55f194f51c966b0db90aa4cbcd02
DIFF: https://github.com/llvm/llvm-project/commit/9f0b736126cb55f194f51c966b0db90aa4cbcd02.diff

LOG: [AMDGPU] Add AGPRs to getRegClassForSizeOnBank

Differential Revision: https://reviews.llvm.org/D79761

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 08d6c97d8158..8a33a13bdbe4 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1720,6 +1720,8 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
                     : &AMDGPU::SReg_64_XEXECRegClass;
   case AMDGPU::SGPRRegBankID:
     return getSGPRClassForBitWidth(std::max(32u, Size));
+  case AMDGPU::AGPRRegBankID:
+    return getAGPRClassForBitWidth(std::max(32u, Size));
   default:
     llvm_unreachable("unknown register bank");
   }