[llvm] 077d2d6 - [CodeGen][SVE] Add patterns for whole vector predicate select
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Tue May 12 03:48:09 PDT 2020
Author: Sander de Smalen
Date: 2020-05-12T11:47:39+01:00
New Revision: 077d2d6802efefe6680cbae78f90e90ef7f04134
URL: https://github.com/llvm/llvm-project/commit/077d2d6802efefe6680cbae78f90e90ef7f04134
DIFF: https://github.com/llvm/llvm-project/commit/077d2d6802efefe6680cbae78f90e90ef7f04134.diff
LOG: [CodeGen][SVE] Add patterns for whole vector predicate select
Added patterns to implement `select i1 %p, <vty> %a, <vty> %b`
Reviewed By: efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79356
Added:
llvm/test/CodeGen/AArch64/select-sve.ll
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 3270ba27d590..899b18f90aee 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -876,6 +876,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
for (MVT VT : MVT::integer_scalable_vector_valuetypes()) {
if (isTypeLegal(VT)) {
setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
+ setOperationAction(ISD::SELECT, VT, Custom);
setOperationAction(ISD::SDIV, VT, Custom);
setOperationAction(ISD::UDIV, VT, Custom);
setOperationAction(ISD::SMIN, VT, Custom);
@@ -893,6 +894,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
for (MVT VT : MVT::fp_scalable_vector_valuetypes()) {
if (isTypeLegal(VT)) {
setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
+ setOperationAction(ISD::SELECT, VT, Custom);
}
}
}
@@ -5710,6 +5712,14 @@ SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
SDValue FVal = Op->getOperand(2);
SDLoc DL(Op);
+ EVT Ty = Op.getValueType();
+ if (Ty.isScalableVector()) {
+ SDValue TruncCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, CCVal);
+ MVT PredVT = MVT::getVectorVT(MVT::i1, Ty.getVectorElementCount());
+ SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, TruncCC);
+ return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal);
+ }
+
// Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
// instruction.
if (ISD::isOverflowIntrOpRes(CCVal)) {
diff --git a/llvm/test/CodeGen/AArch64/select-sve.ll b/llvm/test/CodeGen/AArch64/select-sve.ll
new file mode 100644
index 000000000000..b0959d215161
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/select-sve.ll
@@ -0,0 +1,134 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 16 x i8> @select_nxv16i8(i1 %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: select_nxv16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.b, xzr, x8
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b
+ ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 8 x i16> @select_nxv8i16(i1 %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: select_nxv8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.h, xzr, x8
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b
+ ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @select_nxv4i32(i1 %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: select_nxv4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.s, xzr, x8
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b
+ ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @select_nxv2i64(i1 %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: select_nxv2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.d, xzr, x8
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b
+ ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 8 x half> @select_nxv8f16(i1 %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: select_nxv8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.h, xzr, x8
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x float> @select_nxv4f32(i1 %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: select_nxv4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.s, xzr, x8
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b
+ ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x double> @select_nxv2f64(i1 %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: select_nxv2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p0.d, xzr, x8
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b
+ ret <vscale x 2 x double> %res
+}
+
+define <vscale x 16 x i1> @select_nxv16i1(i1 %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: select_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p2.b, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @select_nxv8i1(i1 %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: select_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p2.h, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @select_nxv4i1(i1 %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: select_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p2.s, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @select_nxv2i1(i1 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: select_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x8, x0, #0, #1
+; CHECK-NEXT: whilelo p2.d, xzr, x8
+; CHECK-NEXT: sel p0.b, p2, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = select i1 %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b
+ ret <vscale x 2 x i1> %res
+}
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