[llvm] 2e9f115 - [x86/SLH][NFC] Add a test to produce a failed generation.

[via llvm-commits]

Author: Wang, Pengfei
Date: 2020-05-12T11:43:20+08:00
New Revision: 2e9f1153c5d467ea1067e3744345a4e1ea2e9bc3

URL: https://github.com/llvm/llvm-project/commit/2e9f1153c5d467ea1067e3744345a4e1ea2e9bc3
DIFF: https://github.com/llvm/llvm-project/commit/2e9f1153c5d467ea1067e3744345a4e1ea2e9bc3.diff

LOG: [x86/SLH][NFC] Add a test to produce a failed generation.

Added: 
    llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
new file mode 100644
index 000000000000..bfc28469281b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -x86-speculative-load-hardening | FileCheck %s
+
+define i32 @foo(void ()** %0) {
+; CHECK-LABEL: foo:
+; CHECK-NOT:    .Lslh_ret_addr0:
+; CHECK:         callq *(%{{.*}})
+; CHECK-NEXT:    movq %rsp, %rcx
+; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT:    sarq $63, %rcx
+; CHECK-NEXT:    cmpq $.Lslh_ret_addr0, %rax
+  %2 = load void ()*, void ()** %0
+  call void asm sideeffect "", "~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"()
+  call void %2()
+  ret i32 0
+}