[PATCH] D79712: [AArch64][BFloat] add BFloat instruction support for AArch64

[Ties Stuij via Phabricator via llvm-commits]

stuij created this revision.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
stuij added a parent revision: D79709: [AArch64][BFloat] basic AArch64 bfloat support.
stuij added a child revision: D79710: [clangd][BFloat] add create/set/get/dup intrinsics.

Add support for lowering various BFloat related SelDAG nodes:

- load/store (ldrh/strh)
- concat
- dup/duplane
- bitconvert/bitcast
- insert_subvector/insert_subreg

This patch is part of a series implementing the Bfloat16 extension of the
Armv8.6-a architecture, as detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

The bfloat type, and its properties is specified in the Arm C language
extension specification:

https://developer.arm.com/docs/ihi0055/d/procedure-call-standard-for-the-arm-64-bit-architecture


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79712

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td

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