[PATCH] D78272: [PowerPC] DAG Combine to transform shifts into multiply-high

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D78272#2025841 <https://reviews.llvm.org/D78272#2025841>, @amyk wrote:

> @craig.topper Do you think common-ing out the X86/PPC parts to combine to mulh into the target independent combiner is a good idea?


I see a few issues.

X86 doesn't have scalar MULHU/MULHS instructions, but we have vector MULHU/MULHS on vXi16. We currently match from truncate rather than from shift. I tried to move it to shift following your code here, but I got regressions. Primarily because we handled the truncate first and turned into PACKSS/PACKUS, may an AND or SIGN_EXTEND_INREG, and some subvector extracts.. Then we match the MULH, but we couldn't fold away the sext/zext and what we had turned the truncate into. We might be able to improve that.   I think it is useful to match from the shift since the truncate won't always be there. So we might need matching from both.

The other issue is that for vectors we need to match for vectors width more than the legal number of elements before type legalization. Otherwise the extends we match get type legalized into something much harder to match. But checking isOperationLegal won't work for that. Maybe we could walk the type legalization steps to find what it would be legalized to?


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https://reviews.llvm.org/D78272