[PATCH] D79037: [StructurizeCFG] Fix region nodes ordering

[Sameer Sahasrabuddhe via Phabricator via llvm-commits]

sameerds added a comment.

In D79037#2024745 <https://reviews.llvm.org/D79037#2024745>, @ekatz wrote:

> In D79037#2024574 <https://reviews.llvm.org/D79037#2024574>, @sameerds wrote:
>
> > Actually, I take that back. Consider the following CFG:
> >
> > A -> H1, H2
> >  H1->B, C
> >  B->H1
> >  C->B, H2
> >  H2->E
> >  E->H2, F
> > 
> >  A is the entry and F is the exit. The loops (H1, B, C) and (H2, E) are siblings with backedges B->H1 and E->H2 respectively. C is an exiting block in the first loop that branches to H2. One POT would be "B, F, E, H2, C, H1, A". When iterating in reverse, the loop with H1 is started first, but H2 from the second loop is encountered before the first loop is completed. 
>
>
> In this case, those loops are in different regions, and as this is a region pass, they won't appear in the same POT.




You need to look at the larger pattern than just the specific example. It should be possible to add exits in both loops that force them into the same region. For example, H2->F and B->F.


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