[PATCH] D79543: [RISCV] Enable 'undisturbed' semantics in instruction definitions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
HsiangKai added reviewers: rogfer01, rkruppe, kito-cheng, evandro, khchen, simoncook.
Herald added subscribers: luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, niosHD, sabuasal, johnrusso, rbar, asb, hiraditya.
Herald added a project: LLVM.

In RISC-V V specification, 'undisturbed' means the values of destination registers will not be changed. There are two scenarios there will be 'undisturbed' elements. One is for tail elements and the other is masked off elements. If the instructions have 'undisturbed' semantics, destination register is also one of the inputs of the instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79543

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td

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