[PATCH] D79521: [RISCV] Add SiFive's interrupt modes

[Ana Pazos via Phabricator via llvm-commits]

apazos created this revision.
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Herald added a project: LLVM.

RISC-V already has support for all the standard interrupt modes:
void f (void) _attribute_ ((interrupt ("machine")));
void f (void) _attribute_ ((interrupt ("user")));
void f (void) _attribute_ ((interrupt ("supervisor")));

This patch adds SiFive's interrupt modes which are available in SiFive's IP.

Reference: https://sifive.cdn.prismic.io/sifive/d1984d2b-c9b9-4c91-8de0-d68a5e64fa0f_sifive-interrupt-cookbook-v1p2.pdf

"SiFive-CLIC-preemptible"
void f (void) _attribute_ ((interrupt ("SiFive-CLIC-preemptible")));
In this type of interrupt handler, in the prologue, the mepc and mcause
registers are saved, and interrupts are enabled.  In the epilogue,
interrupts are disabled, and the mepc and mcause registers are restored.
This type of interrupt handler must be @code{machine} mode,and must not
use the frame pointer.

"SiFive-CLIC-stack-swap"
void f (void) _attribute_ ((interrupt ("SiFive-CLIC-stack-swap")));
In this type of interrupt handler, the stack pointer will be swapped with
the @code{mscratch} register in the prologue before the first use of the stack
pointer, and in the epilogue after the last use of the stack pointer.
This type of interrupt handler must be @code{machine} mode.


https://reviews.llvm.org/D79521

Files:
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/Sema/riscv-interrupt-attr.c
  clang/test/Sema/riscv-sifive-interrupt-attr.c
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll

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