[PATCH] D77767: Prevent register coalescing in functions whith setjmp

[Reid Kleckner via Phabricator via llvm-commits]

rnk added inline comments.


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Comment at: llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir:17
+# Not changed between setjmp and bar(longjmp)
+# CHECK-NOT: %{{[0-9]+}}:dpr, %[[R2]]:gpr = VLD1d32wb_fixed %[[R2]], 0,
+# CHECK: BL @_Z3barPx3S37{{.*}}
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I can't read ARM assembly well enough to tell if this is a good test or to suggest how to make it better, so I'll have to ask Eli to review.


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Comment at: llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll:376
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr5(%rip), %rcx
-; X64-NOPIC-MCM-NEXT:    cmpq %rcx, %r12
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Seems like we don't want to lose these labels. See rGe3ea164659ff37cb4db623c33de880e91aa29ebb. Please regenerate with --no_x86_scrub_rip.

For a while, I have wanted update_llc_test checks to store this option in the comment at the beginning of the file and then read the options back out when regenerating test cases, but it has not come to pass.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77767/new/

https://reviews.llvm.org/D77767