[llvm] b856ff9 - [AMDGPU] Added 'a' constraint documentation. NFC.

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2020-05-05T13:52:04-07:00
New Revision: b856ff97824b6de5fff5b8a418f24f4fc78ba981

URL: https://github.com/llvm/llvm-project/commit/b856ff97824b6de5fff5b8a418f24f4fc78ba981
DIFF: https://github.com/llvm/llvm-project/commit/b856ff97824b6de5fff5b8a418f24f4fc78ba981.diff

LOG: [AMDGPU] Added 'a' constraint documentation. NFC.

AGPR inline asm constraint was missing from the LangRef.rst.

Added: 
    

Modified: 
    llvm/docs/LangRef.rst

Removed: 
    


################################################################################
diff  --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 0bcb7cda76db..fdec9ceaa9c9 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -4104,6 +4104,7 @@ AMDGPU:
 - ``r``: A 32 or 64-bit integer register.
 - ``[0-9]v``: The 32-bit VGPR register, number 0-9.
 - ``[0-9]s``: The 32-bit SGPR register, number 0-9.
+- ``[0-9]a``: The 32-bit AGPR register, number 0-9.
 
 
 All ARM modes: