[PATCH] D79356: [CodeGen][SVE] Add patterns for whole vector predicate select

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

In D79356#2018893 <https://reviews.llvm.org/D79356#2018893>, @efriedma wrote:

> We use whilelo to lower VECTOR_SPLAT; I think that ends up being one fewer vector instruction.  What's the tradeoff between that vs. dup+cmpne?


There's no specific reason to choose dup+cmpne, other than that in these patterns the GPR32 can be any non-zero value, where to use whilelo we'd need a sign-extended i1 value.
I'm happy to change it to use whilelo, but I think it then needs to be implemented in ISelLowering code where we can do analysis on the value of the predicate using `computeKnownBits`, rather than using patterns. Is that correct?


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