[PATCH] D78764: [RISCV] Update debug scratch register names

Pengxuan Zheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 5 09:08:59 PDT 2020


This revision was automatically updated to reflect the committed changes.
Closed by commit rG85aff8a4e49d: [RISCV] Update debug scratch register names (authored by pzheng).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78764/new/

https://reviews.llvm.org/D78764

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/MC/RISCV/machine-csr-names.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D78764.262133.patch
Type: text/x-patch
Size: 4286 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200505/e455a2c8/attachment.bin>


More information about the llvm-commits mailing list