[PATCH] D79402: [ARM] Correct the type on a predicate cast

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added a reviewer: simon_tatham.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
dmgreen added reviewers: SjoerdMeijer, samparker, ostannard.

A PREDICATE_CAST(PREDICATE_CAST(X)) can be converted to a PREDICATE_CAST(X) as the operation can convert between any forms of predicates (v4i1/v8i1/v16i1/i32). Unfortunately I got the type wrong on one of the rarer converts, which would lead to invalid nodes during isel. This fixes it up to the correct type.


https://reviews.llvm.org/D79402

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/Thumb2/mve-pred-convert.ll


Index: llvm/test/CodeGen/Thumb2/mve-pred-convert.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/mve-pred-convert.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
+
+define void @g(i8* %v) {
+; CHECK-LABEL: g:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    movs r0, #63
+; CHECK-NEXT:    vmov.i32 q0, #0x0
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vpst
+; CHECK-NEXT:    vstrbt.8 q0, [r0]
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = load i8, i8* %v, align 1
+  %conv = zext i8 %0 to i32
+  %broadcast.splatinsert = insertelement <16 x i32> undef, i32 %conv, i32 0
+  %broadcast.splat = shufflevector <16 x i32> %broadcast.splatinsert, <16 x i32> undef, <16 x i32> zeroinitializer
+  %1 = and <16 x i32> %broadcast.splat, <i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 512, i32 1024, i32 2048, i32 4096, i32 8192, i32 16384, i32 32768>
+  %2 = icmp eq <16 x i32> %1, zeroinitializer
+  %3 = select <16 x i1> %2, <16 x i8> zeroinitializer, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>
+  call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %3, <16 x i8>* undef, i32 1, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>)
+  ret void
+}
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>) #1
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13180,8 +13180,7 @@
     // If the valuetypes are the same, we can remove the cast entirely.
     if (Op->getOperand(0).getValueType() == VT)
       return Op->getOperand(0);
-    return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl,
-                           Op->getOperand(0).getValueType(), Op->getOperand(0));
+    return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
   }
 
   return SDValue();


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D79402.262028.patch
Type: text/x-patch
Size: 2387 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200505/8111670e/attachment.bin>