[llvm] 7d572ef - Revert "[SCEV] rewriteLoopExitValues(): even if have hard uses, still rewrite if cheap (PR44668)"
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Mon May 4 10:26:50 PDT 2020
(hit send slightly too soon)
On 5/4/20 10:25 AM, Philip Reames wrote:
> Belated, but...
>
> I'm really sad to see this being backed out. I really do think that
> being aggressive on loop exit value rewriting is the right default. I
> agree that we probably need a reverse transform, but I'd have
> preferred to see this left in while that was worked on. While there
> was a reported regression, it appears to have been fairly isolated.
> Reading through the review, I don't see evidence of a reproducer being
> provided even. That wouldn't raise to the level of justifying a
> revert to me.
>
> Not asking that you change course or anything, just sharing my view.
Regardless, thank you for your work on this. The cost modeling changes
alone were highly valuable. Thank you for taking that on.
>
> Philip
>
> On 4/3/20 10:15 AM, Roman Lebedev via llvm-commits wrote:
>> Author: Roman Lebedev
>> Date: 2020-04-03T20:15:04+03:00
>> New Revision: 7d572ef2dd9bf68d56c0fa3152c2dea2f778f147
>>
>> URL:
>> https://github.com/llvm/llvm-project/commit/7d572ef2dd9bf68d56c0fa3152c2dea2f778f147
>> DIFF:
>> https://github.com/llvm/llvm-project/commit/7d572ef2dd9bf68d56c0fa3152c2dea2f778f147.diff
>>
>> LOG: Revert "[SCEV] rewriteLoopExitValues(): even if have hard uses,
>> still rewrite if cheap (PR44668)"
>>
>> As discussed in post-commit review in https://reviews.llvm.org/D73501
>> if the goal of this is to help vectorizer, then we should actually
>> be teaching vectorizer to do this, because right now this rewrite
>> is still budget-limited, which isn't what we'd want.
>>
>> Additionally, while the rest of the patch series was universally
>> profitable,
>> this particular patch is reportedly
>> (https://reviews.llvm.org/D73501#1905171)
>> exposing cost-modeling issues on ARM.
>>
>> So let's just back this particular patch out. Once there's an undo
>> transform,
>> this could be considered for reintegration.
>>
>> This reverts commit 44edc6fd2c63b7db43e13cc8caf1fee79bebdb5f.
>>
>> Added:
>> llvm/test/Transforms/IndVarSimplify/dont-recompute.ll
>>
>> Modified:
>> llvm/lib/Transforms/Utils/LoopUtils.cpp
>> llvm/test/Transforms/IndVarSimplify/ARM/indvar-cost.ll
>> llvm/test/Transforms/IndVarSimplify/elim-extend.ll
>> llvm/test/Transforms/IndVarSimplify/lrev-existing-umin.ll
>> llvm/test/Transforms/IndVarSimplify/pr28705.ll
>> llvm/test/Transforms/IndVarSimplify/pr39673.ll
>>
>> Removed:
>> llvm/test/Transforms/IndVarSimplify/do-recompute-if-cheap.ll
>>
>>
>> ################################################################################
>>
>> diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp
>> b/llvm/lib/Transforms/Utils/LoopUtils.cpp
>> index b86a67faf646..73e5ac4271a1 100644
>> --- a/llvm/lib/Transforms/Utils/LoopUtils.cpp
>> +++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp
>> @@ -1359,16 +1359,15 @@ int llvm::rewriteLoopExitValues(Loop *L,
>> LoopInfo *LI, TargetLibraryInfo *TLI,
>> // Computing the value outside of the loop brings no
>> benefit if it is
>> // definitely used inside the loop in a way which can not
>> be optimized
>> - // away. Avoid doing so unless either we know we have a value
>> - // which computes the ExitValue already, or it is cheap to
>> do so.
>> - // TODO: This should be merged into SCEV expander to leverage
>> - // its knowledge of existing expressions.
>> - bool HighCost = Rewriter.isHighCostExpansion(
>> - ExitValue, L, SCEVCheapExpansionBudget, TTI, Inst);
>> - if (ReplaceExitValue != AlwaysRepl && HighCost &&
>> - hasHardUserWithinLoop(L, Inst))
>> + // away. Avoid doing so unless we know we have a value which
>> computes
>> + // the ExitValue already. TODO: This should be merged into SCEV
>> + // expander to leverage its knowledge of existing expressions.
>> + if (ReplaceExitValue != AlwaysRepl &&
>> !isa<SCEVConstant>(ExitValue) &&
>> + !isa<SCEVUnknown>(ExitValue) && hasHardUserWithinLoop(L,
>> Inst))
>> continue;
>> + bool HighCost = Rewriter.isHighCostExpansion(
>> + ExitValue, L, SCEVCheapExpansionBudget, TTI, Inst);
>> Value *ExitVal = Rewriter.expandCodeFor(ExitValue,
>> PN->getType(), Inst);
>> LLVM_DEBUG(dbgs() << "rewriteLoopExitValues: AfterLoopVal
>> = "
>>
>> diff --git a/llvm/test/Transforms/IndVarSimplify/ARM/indvar-cost.ll
>> b/llvm/test/Transforms/IndVarSimplify/ARM/indvar-cost.ll
>> index df4c71777b96..14d873d9e3ac 100644
>> --- a/llvm/test/Transforms/IndVarSimplify/ARM/indvar-cost.ll
>> +++ b/llvm/test/Transforms/IndVarSimplify/ARM/indvar-cost.ll
>> @@ -13,9 +13,6 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T1-NEXT: [[CMP41080:%.*]] = icmp eq i32 [[SUB]], 0
>> ; CHECK-T1-NEXT: br i1 [[CMP41080]], label [[WHILE_END13:%.*]],
>> label [[WHILE_COND5_PREHEADER_PREHEADER:%.*]]
>> ; CHECK-T1: while.cond5.preheader.preheader:
>> -; CHECK-T1-NEXT: [[TMP0:%.*]] = add i32 [[SRCALEN_SRCBLEN]], -2
>> -; CHECK-T1-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], 2
>> -; CHECK-T1-NEXT: [[UMIN:%.*]] = select i1 [[TMP1]], i32 [[TMP0]],
>> i32 2
>> ; CHECK-T1-NEXT: br label [[WHILE_COND5_PREHEADER:%.*]]
>> ; CHECK-T1: while.cond5.preheader:
>> ; CHECK-T1-NEXT: [[COUNT_01084:%.*]] = phi i32 [ [[INC:%.*]],
>> [[WHILE_END:%.*]] ], [ 1, [[WHILE_COND5_PREHEADER_PREHEADER]] ]
>> @@ -29,11 +26,11 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T1-NEXT: [[PY_11076:%.*]] = phi i16* [
>> [[INCDEC_PTR8:%.*]], [[WHILE_BODY7]] ], [ [[PY_01082]],
>> [[WHILE_COND5_PREHEADER]] ]
>> ; CHECK-T1-NEXT: [[PX_11075:%.*]] = phi i16* [
>> [[INCDEC_PTR:%.*]], [[WHILE_BODY7]] ], [ [[PSRCB_PSRCA]],
>> [[WHILE_COND5_PREHEADER]] ]
>> ; CHECK-T1-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i16,
>> i16* [[PX_11075]], i32 1
>> -; CHECK-T1-NEXT: [[TMP2:%.*]] = load i16, i16* [[PX_11075]], align 2
>> -; CHECK-T1-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32
>> +; CHECK-T1-NEXT: [[TMP0:%.*]] = load i16, i16* [[PX_11075]], align 2
>> +; CHECK-T1-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
>> ; CHECK-T1-NEXT: [[INCDEC_PTR8]] = getelementptr inbounds i16,
>> i16* [[PY_11076]], i32 -1
>> -; CHECK-T1-NEXT: [[TMP3:%.*]] = load i16, i16* [[PY_11076]], align 2
>> -; CHECK-T1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP3]] to i32
>> +; CHECK-T1-NEXT: [[TMP1:%.*]] = load i16, i16* [[PY_11076]], align 2
>> +; CHECK-T1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
>> ; CHECK-T1-NEXT: [[MUL_I:%.*]] = mul nsw i32 [[CONV9]], [[CONV]]
>> ; CHECK-T1-NEXT: [[SHR3_I:%.*]] = ashr i32 [[CONV]], 16
>> ; CHECK-T1-NEXT: [[SHR4_I:%.*]] = ashr i32 [[CONV9]], 16
>> @@ -45,8 +42,8 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T1-NEXT: br i1 [[CMP6]], label [[WHILE_END]], label
>> [[WHILE_BODY7]]
>> ; CHECK-T1: while.end:
>> ; CHECK-T1-NEXT: [[ADD6_I_LCSSA:%.*]] = phi i32 [ [[ADD6_I]],
>> [[WHILE_BODY7]] ]
>> -; CHECK-T1-NEXT: [[TMP4:%.*]] = lshr i32 [[ADD6_I_LCSSA]], 15
>> -; CHECK-T1-NEXT: [[CONV10:%.*]] = trunc i32 [[TMP4]] to i16
>> +; CHECK-T1-NEXT: [[TMP2:%.*]] = lshr i32 [[ADD6_I_LCSSA]], 15
>> +; CHECK-T1-NEXT: [[CONV10:%.*]] = trunc i32 [[TMP2]] to i16
>> ; CHECK-T1-NEXT: [[INCDEC_PTR11]] = getelementptr inbounds i16,
>> i16* [[POUT_01081]], i32 1
>> ; CHECK-T1-NEXT: store i16 [[CONV10]], i16* [[POUT_01081]], align 2
>> ; CHECK-T1-NEXT: [[ADD_PTR]] = getelementptr inbounds i16, i16*
>> [[PSRCA_PSRCB]], i32 [[COUNT_01084]]
>> @@ -54,19 +51,19 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T1-NEXT: [[DEC12]] = add i32 [[BLOCKSIZE1_01083]], -1
>> ; CHECK-T1-NEXT: [[CMP3:%.*]] = icmp ult i32 [[COUNT_01084]], 3
>> ; CHECK-T1-NEXT: [[CMP4:%.*]] = icmp ne i32 [[DEC12]], 0
>> -; CHECK-T1-NEXT: [[TMP5:%.*]] = and i1 [[CMP4]], [[CMP3]]
>> -; CHECK-T1-NEXT: br i1 [[TMP5]], label [[WHILE_COND5_PREHEADER]],
>> label [[WHILE_END13_LOOPEXIT:%.*]]
>> +; CHECK-T1-NEXT: [[TMP3:%.*]] = and i1 [[CMP4]], [[CMP3]]
>> +; CHECK-T1-NEXT: br i1 [[TMP3]], label [[WHILE_COND5_PREHEADER]],
>> label [[WHILE_END13_LOOPEXIT:%.*]]
>> ; CHECK-T1: while.end13.loopexit:
>> ; CHECK-T1-NEXT: [[INCDEC_PTR11_LCSSA:%.*]] = phi i16* [
>> [[INCDEC_PTR11]], [[WHILE_END]] ]
>> ; CHECK-T1-NEXT: [[ADD_PTR_LCSSA:%.*]] = phi i16* [ [[ADD_PTR]],
>> [[WHILE_END]] ]
>> +; CHECK-T1-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]],
>> [[WHILE_END]] ]
>> ; CHECK-T1-NEXT: [[DEC12_LCSSA:%.*]] = phi i32 [ [[DEC12]],
>> [[WHILE_END]] ]
>> -; CHECK-T1-NEXT: [[TMP6:%.*]] = add nuw nsw i32 [[UMIN]], 2
>> ; CHECK-T1-NEXT: br label [[WHILE_END13]]
>> ; CHECK-T1: while.end13:
>> ; CHECK-T1-NEXT: [[POUT_0_LCSSA:%.*]] = phi i16* [ [[PDST]],
>> [[ENTRY:%.*]] ], [ [[INCDEC_PTR11_LCSSA]], [[WHILE_END13_LOOPEXIT]] ]
>> ; CHECK-T1-NEXT: [[PY_0_LCSSA:%.*]] = phi i16* [
>> [[PSRCA_PSRCB]], [[ENTRY]] ], [ [[ADD_PTR_LCSSA]],
>> [[WHILE_END13_LOOPEXIT]] ]
>> ; CHECK-T1-NEXT: [[BLOCKSIZE1_0_LCSSA:%.*]] = phi i32 [ [[SUB]],
>> [[ENTRY]] ], [ [[DEC12_LCSSA]], [[WHILE_END13_LOOPEXIT]] ]
>> -; CHECK-T1-NEXT: [[COUNT_0_LCSSA:%.*]] = phi i32 [ 1, [[ENTRY]]
>> ], [ [[TMP6]], [[WHILE_END13_LOOPEXIT]] ]
>> +; CHECK-T1-NEXT: [[COUNT_0_LCSSA:%.*]] = phi i32 [ 1, [[ENTRY]]
>> ], [ [[INC_LCSSA]], [[WHILE_END13_LOOPEXIT]] ]
>> ; CHECK-T1-NEXT: [[CMP161068:%.*]] = icmp eq i32
>> [[BLOCKSIZE1_0_LCSSA]], 0
>> ; CHECK-T1-NEXT: br i1 [[CMP161068]], label [[EXIT:%.*]], label
>> [[WHILE_BODY18_PREHEADER:%.*]]
>> ; CHECK-T1: while.body18.preheader:
>> @@ -88,34 +85,34 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T1-NEXT: [[PY_31056:%.*]] = phi i16* [
>> [[ADD_PTR_I884:%.*]], [[WHILE_BODY23]] ], [ [[PY_21070]],
>> [[WHILE_BODY23_PREHEADER]] ]
>> ; CHECK-T1-NEXT: [[PX_31055:%.*]] = phi i16* [
>> [[ADD_PTR_I890:%.*]], [[WHILE_BODY23]] ], [ [[PSRCB_PSRCA]],
>> [[WHILE_BODY23_PREHEADER]] ]
>> ; CHECK-T1-NEXT: [[ARRAYIDX_I907:%.*]] = getelementptr inbounds
>> i16, i16* [[PX_31055]], i32 1
>> -; CHECK-T1-NEXT: [[TMP7:%.*]] = load i16, i16* [[ARRAYIDX_I907]],
>> align 2
>> -; CHECK-T1-NEXT: [[TMP8:%.*]] = load i16, i16* [[PX_31055]], align 2
>> +; CHECK-T1-NEXT: [[TMP4:%.*]] = load i16, i16* [[ARRAYIDX_I907]],
>> align 2
>> +; CHECK-T1-NEXT: [[TMP5:%.*]] = load i16, i16* [[PX_31055]], align 2
>> ; CHECK-T1-NEXT: [[ADD_PTR_I912:%.*]] = getelementptr inbounds
>> i16, i16* [[PX_31055]], i32 2
>> ; CHECK-T1-NEXT: [[ARRAYIDX_I901:%.*]] = getelementptr inbounds
>> i16, i16* [[PY_31056]], i32 1
>> -; CHECK-T1-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX_I901]],
>> align 2
>> -; CHECK-T1-NEXT: [[TMP10:%.*]] = load i16, i16* [[PY_31056]],
>> align 2
>> +; CHECK-T1-NEXT: [[TMP6:%.*]] = load i16, i16* [[ARRAYIDX_I901]],
>> align 2
>> +; CHECK-T1-NEXT: [[TMP7:%.*]] = load i16, i16* [[PY_31056]], align 2
>> ; CHECK-T1-NEXT: [[ADD_PTR_I906:%.*]] = getelementptr inbounds
>> i16, i16* [[PY_31056]], i32 -2
>> -; CHECK-T1-NEXT: [[SHR_I892:%.*]] = sext i16 [[TMP8]] to i32
>> -; CHECK-T1-NEXT: [[SHR1_I893:%.*]] = sext i16 [[TMP9]] to i32
>> +; CHECK-T1-NEXT: [[SHR_I892:%.*]] = sext i16 [[TMP5]] to i32
>> +; CHECK-T1-NEXT: [[SHR1_I893:%.*]] = sext i16 [[TMP6]] to i32
>> ; CHECK-T1-NEXT: [[MUL_I894:%.*]] = mul nsw i32 [[SHR1_I893]],
>> [[SHR_I892]]
>> -; CHECK-T1-NEXT: [[SHR2_I895:%.*]] = sext i16 [[TMP7]] to i32
>> -; CHECK-T1-NEXT: [[SHR4_I897:%.*]] = sext i16 [[TMP10]] to i32
>> +; CHECK-T1-NEXT: [[SHR2_I895:%.*]] = sext i16 [[TMP4]] to i32
>> +; CHECK-T1-NEXT: [[SHR4_I897:%.*]] = sext i16 [[TMP7]] to i32
>> ; CHECK-T1-NEXT: [[MUL5_I898:%.*]] = mul nsw i32 [[SHR4_I897]],
>> [[SHR2_I895]]
>> ; CHECK-T1-NEXT: [[ADD_I899:%.*]] = add i32 [[MUL_I894]],
>> [[SUM_11057]]
>> ; CHECK-T1-NEXT: [[ADD6_I900:%.*]] = add i32 [[ADD_I899]],
>> [[MUL5_I898]]
>> ; CHECK-T1-NEXT: [[ARRAYIDX_I885:%.*]] = getelementptr inbounds
>> i16, i16* [[PX_31055]], i32 3
>> -; CHECK-T1-NEXT: [[TMP11:%.*]] = load i16, i16*
>> [[ARRAYIDX_I885]], align 2
>> -; CHECK-T1-NEXT: [[TMP12:%.*]] = load i16, i16* [[ADD_PTR_I912]],
>> align 2
>> +; CHECK-T1-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX_I885]],
>> align 2
>> +; CHECK-T1-NEXT: [[TMP9:%.*]] = load i16, i16* [[ADD_PTR_I912]],
>> align 2
>> ; CHECK-T1-NEXT: [[ADD_PTR_I890]] = getelementptr inbounds i16,
>> i16* [[PX_31055]], i32 4
>> ; CHECK-T1-NEXT: [[ARRAYIDX_I879:%.*]] = getelementptr inbounds
>> i16, i16* [[PY_31056]], i32 -1
>> -; CHECK-T1-NEXT: [[TMP13:%.*]] = load i16, i16*
>> [[ARRAYIDX_I879]], align 2
>> -; CHECK-T1-NEXT: [[TMP14:%.*]] = load i16, i16* [[ADD_PTR_I906]],
>> align 2
>> +; CHECK-T1-NEXT: [[TMP10:%.*]] = load i16, i16*
>> [[ARRAYIDX_I879]], align 2
>> +; CHECK-T1-NEXT: [[TMP11:%.*]] = load i16, i16* [[ADD_PTR_I906]],
>> align 2
>> ; CHECK-T1-NEXT: [[ADD_PTR_I884]] = getelementptr inbounds i16,
>> i16* [[PY_31056]], i32 -4
>> -; CHECK-T1-NEXT: [[SHR_I870:%.*]] = sext i16 [[TMP12]] to i32
>> -; CHECK-T1-NEXT: [[SHR1_I871:%.*]] = sext i16 [[TMP13]] to i32
>> +; CHECK-T1-NEXT: [[SHR_I870:%.*]] = sext i16 [[TMP9]] to i32
>> +; CHECK-T1-NEXT: [[SHR1_I871:%.*]] = sext i16 [[TMP10]] to i32
>> ; CHECK-T1-NEXT: [[MUL_I872:%.*]] = mul nsw i32 [[SHR1_I871]],
>> [[SHR_I870]]
>> -; CHECK-T1-NEXT: [[SHR2_I873:%.*]] = sext i16 [[TMP11]] to i32
>> -; CHECK-T1-NEXT: [[SHR4_I875:%.*]] = sext i16 [[TMP14]] to i32
>> +; CHECK-T1-NEXT: [[SHR2_I873:%.*]] = sext i16 [[TMP8]] to i32
>> +; CHECK-T1-NEXT: [[SHR4_I875:%.*]] = sext i16 [[TMP11]] to i32
>> ; CHECK-T1-NEXT: [[MUL5_I876:%.*]] = mul nsw i32 [[SHR4_I875]],
>> [[SHR2_I873]]
>> ; CHECK-T1-NEXT: [[ADD_I877:%.*]] = add i32 [[ADD6_I900]],
>> [[MUL_I872]]
>> ; CHECK-T1-NEXT: [[ADD6_I878]] = add i32 [[ADD_I877]],
>> [[MUL5_I876]]
>> @@ -143,11 +140,11 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T1-NEXT: [[PY_41064:%.*]] = phi i16* [
>> [[INCDEC_PTR39:%.*]], [[WHILE_BODY36]] ], [ [[ADD_PTR32]],
>> [[WHILE_BODY36_PREHEADER]] ]
>> ; CHECK-T1-NEXT: [[PX_41063:%.*]] = phi i16* [
>> [[INCDEC_PTR37:%.*]], [[WHILE_BODY36]] ], [ [[PX_3_LCSSA]],
>> [[WHILE_BODY36_PREHEADER]] ]
>> ; CHECK-T1-NEXT: [[INCDEC_PTR37]] = getelementptr inbounds i16,
>> i16* [[PX_41063]], i32 1
>> -; CHECK-T1-NEXT: [[TMP15:%.*]] = load i16, i16* [[PX_41063]],
>> align 2
>> -; CHECK-T1-NEXT: [[CONV38:%.*]] = sext i16 [[TMP15]] to i32
>> +; CHECK-T1-NEXT: [[TMP12:%.*]] = load i16, i16* [[PX_41063]],
>> align 2
>> +; CHECK-T1-NEXT: [[CONV38:%.*]] = sext i16 [[TMP12]] to i32
>> ; CHECK-T1-NEXT: [[INCDEC_PTR39]] = getelementptr inbounds i16,
>> i16* [[PY_41064]], i32 -1
>> -; CHECK-T1-NEXT: [[TMP16:%.*]] = load i16, i16* [[PY_41064]],
>> align 2
>> -; CHECK-T1-NEXT: [[CONV40:%.*]] = sext i16 [[TMP16]] to i32
>> +; CHECK-T1-NEXT: [[TMP13:%.*]] = load i16, i16* [[PY_41064]],
>> align 2
>> +; CHECK-T1-NEXT: [[CONV40:%.*]] = sext i16 [[TMP13]] to i32
>> ; CHECK-T1-NEXT: [[MUL_I863:%.*]] = mul nsw i32 [[CONV40]],
>> [[CONV38]]
>> ; CHECK-T1-NEXT: [[SHR3_I864:%.*]] = ashr i32 [[CONV38]], 16
>> ; CHECK-T1-NEXT: [[SHR4_I865:%.*]] = ashr i32 [[CONV40]], 16
>> @@ -162,8 +159,8 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T1-NEXT: br label [[WHILE_END43]]
>> ; CHECK-T1: while.end43:
>> ; CHECK-T1-NEXT: [[SUM_2_LCSSA:%.*]] = phi i32 [
>> [[SUM_1_LCSSA]], [[WHILE_END31]] ], [ [[ADD6_I868_LCSSA]],
>> [[WHILE_END43_LOOPEXIT]] ]
>> -; CHECK-T1-NEXT: [[TMP17:%.*]] = lshr i32 [[SUM_2_LCSSA]], 15
>> -; CHECK-T1-NEXT: [[CONV45:%.*]] = trunc i32 [[TMP17]] to i16
>> +; CHECK-T1-NEXT: [[TMP14:%.*]] = lshr i32 [[SUM_2_LCSSA]], 15
>> +; CHECK-T1-NEXT: [[CONV45:%.*]] = trunc i32 [[TMP14]] to i16
>> ; CHECK-T1-NEXT: [[INCDEC_PTR46]] = getelementptr inbounds i16,
>> i16* [[POUT_11069]], i32 1
>> ; CHECK-T1-NEXT: store i16 [[CONV45]], i16* [[POUT_11069]], align 2
>> ; CHECK-T1-NEXT: [[SUB47:%.*]] = add i32 [[COUNT_11072]], -1
>> @@ -187,9 +184,6 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T2-NEXT: [[CMP41080:%.*]] = icmp eq i32 [[SUB]], 0
>> ; CHECK-T2-NEXT: br i1 [[CMP41080]], label [[WHILE_END13:%.*]],
>> label [[WHILE_COND5_PREHEADER_PREHEADER:%.*]]
>> ; CHECK-T2: while.cond5.preheader.preheader:
>> -; CHECK-T2-NEXT: [[TMP0:%.*]] = add i32 [[SRCALEN_SRCBLEN]], -2
>> -; CHECK-T2-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], 2
>> -; CHECK-T2-NEXT: [[UMIN:%.*]] = select i1 [[TMP1]], i32 [[TMP0]],
>> i32 2
>> ; CHECK-T2-NEXT: br label [[WHILE_COND5_PREHEADER:%.*]]
>> ; CHECK-T2: while.cond5.preheader:
>> ; CHECK-T2-NEXT: [[COUNT_01084:%.*]] = phi i32 [ [[INC:%.*]],
>> [[WHILE_END:%.*]] ], [ 1, [[WHILE_COND5_PREHEADER_PREHEADER]] ]
>> @@ -203,11 +197,11 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T2-NEXT: [[PY_11076:%.*]] = phi i16* [
>> [[INCDEC_PTR8:%.*]], [[WHILE_BODY7]] ], [ [[PY_01082]],
>> [[WHILE_COND5_PREHEADER]] ]
>> ; CHECK-T2-NEXT: [[PX_11075:%.*]] = phi i16* [
>> [[INCDEC_PTR:%.*]], [[WHILE_BODY7]] ], [ [[PSRCB_PSRCA]],
>> [[WHILE_COND5_PREHEADER]] ]
>> ; CHECK-T2-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i16,
>> i16* [[PX_11075]], i32 1
>> -; CHECK-T2-NEXT: [[TMP2:%.*]] = load i16, i16* [[PX_11075]], align 2
>> -; CHECK-T2-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32
>> +; CHECK-T2-NEXT: [[TMP0:%.*]] = load i16, i16* [[PX_11075]], align 2
>> +; CHECK-T2-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
>> ; CHECK-T2-NEXT: [[INCDEC_PTR8]] = getelementptr inbounds i16,
>> i16* [[PY_11076]], i32 -1
>> -; CHECK-T2-NEXT: [[TMP3:%.*]] = load i16, i16* [[PY_11076]], align 2
>> -; CHECK-T2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP3]] to i32
>> +; CHECK-T2-NEXT: [[TMP1:%.*]] = load i16, i16* [[PY_11076]], align 2
>> +; CHECK-T2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
>> ; CHECK-T2-NEXT: [[MUL_I:%.*]] = mul nsw i32 [[CONV9]], [[CONV]]
>> ; CHECK-T2-NEXT: [[SHR3_I:%.*]] = ashr i32 [[CONV]], 16
>> ; CHECK-T2-NEXT: [[SHR4_I:%.*]] = ashr i32 [[CONV9]], 16
>> @@ -219,8 +213,8 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T2-NEXT: br i1 [[CMP6]], label [[WHILE_END]], label
>> [[WHILE_BODY7]]
>> ; CHECK-T2: while.end:
>> ; CHECK-T2-NEXT: [[ADD6_I_LCSSA:%.*]] = phi i32 [ [[ADD6_I]],
>> [[WHILE_BODY7]] ]
>> -; CHECK-T2-NEXT: [[TMP4:%.*]] = lshr i32 [[ADD6_I_LCSSA]], 15
>> -; CHECK-T2-NEXT: [[CONV10:%.*]] = trunc i32 [[TMP4]] to i16
>> +; CHECK-T2-NEXT: [[TMP2:%.*]] = lshr i32 [[ADD6_I_LCSSA]], 15
>> +; CHECK-T2-NEXT: [[CONV10:%.*]] = trunc i32 [[TMP2]] to i16
>> ; CHECK-T2-NEXT: [[INCDEC_PTR11]] = getelementptr inbounds i16,
>> i16* [[POUT_01081]], i32 1
>> ; CHECK-T2-NEXT: store i16 [[CONV10]], i16* [[POUT_01081]], align 2
>> ; CHECK-T2-NEXT: [[ADD_PTR]] = getelementptr inbounds i16, i16*
>> [[PSRCA_PSRCB]], i32 [[COUNT_01084]]
>> @@ -228,19 +222,19 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T2-NEXT: [[DEC12]] = add i32 [[BLOCKSIZE1_01083]], -1
>> ; CHECK-T2-NEXT: [[CMP3:%.*]] = icmp ult i32 [[COUNT_01084]], 3
>> ; CHECK-T2-NEXT: [[CMP4:%.*]] = icmp ne i32 [[DEC12]], 0
>> -; CHECK-T2-NEXT: [[TMP5:%.*]] = and i1 [[CMP4]], [[CMP3]]
>> -; CHECK-T2-NEXT: br i1 [[TMP5]], label [[WHILE_COND5_PREHEADER]],
>> label [[WHILE_END13_LOOPEXIT:%.*]]
>> +; CHECK-T2-NEXT: [[TMP3:%.*]] = and i1 [[CMP4]], [[CMP3]]
>> +; CHECK-T2-NEXT: br i1 [[TMP3]], label [[WHILE_COND5_PREHEADER]],
>> label [[WHILE_END13_LOOPEXIT:%.*]]
>> ; CHECK-T2: while.end13.loopexit:
>> ; CHECK-T2-NEXT: [[INCDEC_PTR11_LCSSA:%.*]] = phi i16* [
>> [[INCDEC_PTR11]], [[WHILE_END]] ]
>> ; CHECK-T2-NEXT: [[ADD_PTR_LCSSA:%.*]] = phi i16* [ [[ADD_PTR]],
>> [[WHILE_END]] ]
>> +; CHECK-T2-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]],
>> [[WHILE_END]] ]
>> ; CHECK-T2-NEXT: [[DEC12_LCSSA:%.*]] = phi i32 [ [[DEC12]],
>> [[WHILE_END]] ]
>> -; CHECK-T2-NEXT: [[TMP6:%.*]] = add nuw nsw i32 [[UMIN]], 2
>> ; CHECK-T2-NEXT: br label [[WHILE_END13]]
>> ; CHECK-T2: while.end13:
>> ; CHECK-T2-NEXT: [[POUT_0_LCSSA:%.*]] = phi i16* [ [[PDST]],
>> [[ENTRY:%.*]] ], [ [[INCDEC_PTR11_LCSSA]], [[WHILE_END13_LOOPEXIT]] ]
>> ; CHECK-T2-NEXT: [[PY_0_LCSSA:%.*]] = phi i16* [
>> [[PSRCA_PSRCB]], [[ENTRY]] ], [ [[ADD_PTR_LCSSA]],
>> [[WHILE_END13_LOOPEXIT]] ]
>> ; CHECK-T2-NEXT: [[BLOCKSIZE1_0_LCSSA:%.*]] = phi i32 [ [[SUB]],
>> [[ENTRY]] ], [ [[DEC12_LCSSA]], [[WHILE_END13_LOOPEXIT]] ]
>> -; CHECK-T2-NEXT: [[COUNT_0_LCSSA:%.*]] = phi i32 [ 1, [[ENTRY]]
>> ], [ [[TMP6]], [[WHILE_END13_LOOPEXIT]] ]
>> +; CHECK-T2-NEXT: [[COUNT_0_LCSSA:%.*]] = phi i32 [ 1, [[ENTRY]]
>> ], [ [[INC_LCSSA]], [[WHILE_END13_LOOPEXIT]] ]
>> ; CHECK-T2-NEXT: [[CMP161068:%.*]] = icmp eq i32
>> [[BLOCKSIZE1_0_LCSSA]], 0
>> ; CHECK-T2-NEXT: br i1 [[CMP161068]], label [[EXIT:%.*]], label
>> [[WHILE_BODY18_PREHEADER:%.*]]
>> ; CHECK-T2: while.body18.preheader:
>> @@ -262,34 +256,34 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T2-NEXT: [[PY_31056:%.*]] = phi i16* [
>> [[ADD_PTR_I884:%.*]], [[WHILE_BODY23]] ], [ [[PY_21070]],
>> [[WHILE_BODY23_PREHEADER]] ]
>> ; CHECK-T2-NEXT: [[PX_31055:%.*]] = phi i16* [
>> [[ADD_PTR_I890:%.*]], [[WHILE_BODY23]] ], [ [[PSRCB_PSRCA]],
>> [[WHILE_BODY23_PREHEADER]] ]
>> ; CHECK-T2-NEXT: [[ARRAYIDX_I907:%.*]] = getelementptr inbounds
>> i16, i16* [[PX_31055]], i32 1
>> -; CHECK-T2-NEXT: [[TMP7:%.*]] = load i16, i16* [[ARRAYIDX_I907]],
>> align 2
>> -; CHECK-T2-NEXT: [[TMP8:%.*]] = load i16, i16* [[PX_31055]], align 2
>> +; CHECK-T2-NEXT: [[TMP4:%.*]] = load i16, i16* [[ARRAYIDX_I907]],
>> align 2
>> +; CHECK-T2-NEXT: [[TMP5:%.*]] = load i16, i16* [[PX_31055]], align 2
>> ; CHECK-T2-NEXT: [[ADD_PTR_I912:%.*]] = getelementptr inbounds
>> i16, i16* [[PX_31055]], i32 2
>> ; CHECK-T2-NEXT: [[ARRAYIDX_I901:%.*]] = getelementptr inbounds
>> i16, i16* [[PY_31056]], i32 1
>> -; CHECK-T2-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX_I901]],
>> align 2
>> -; CHECK-T2-NEXT: [[TMP10:%.*]] = load i16, i16* [[PY_31056]],
>> align 2
>> +; CHECK-T2-NEXT: [[TMP6:%.*]] = load i16, i16* [[ARRAYIDX_I901]],
>> align 2
>> +; CHECK-T2-NEXT: [[TMP7:%.*]] = load i16, i16* [[PY_31056]], align 2
>> ; CHECK-T2-NEXT: [[ADD_PTR_I906:%.*]] = getelementptr inbounds
>> i16, i16* [[PY_31056]], i32 -2
>> -; CHECK-T2-NEXT: [[SHR_I892:%.*]] = sext i16 [[TMP8]] to i32
>> -; CHECK-T2-NEXT: [[SHR1_I893:%.*]] = sext i16 [[TMP9]] to i32
>> +; CHECK-T2-NEXT: [[SHR_I892:%.*]] = sext i16 [[TMP5]] to i32
>> +; CHECK-T2-NEXT: [[SHR1_I893:%.*]] = sext i16 [[TMP6]] to i32
>> ; CHECK-T2-NEXT: [[MUL_I894:%.*]] = mul nsw i32 [[SHR1_I893]],
>> [[SHR_I892]]
>> -; CHECK-T2-NEXT: [[SHR2_I895:%.*]] = sext i16 [[TMP7]] to i32
>> -; CHECK-T2-NEXT: [[SHR4_I897:%.*]] = sext i16 [[TMP10]] to i32
>> +; CHECK-T2-NEXT: [[SHR2_I895:%.*]] = sext i16 [[TMP4]] to i32
>> +; CHECK-T2-NEXT: [[SHR4_I897:%.*]] = sext i16 [[TMP7]] to i32
>> ; CHECK-T2-NEXT: [[MUL5_I898:%.*]] = mul nsw i32 [[SHR4_I897]],
>> [[SHR2_I895]]
>> ; CHECK-T2-NEXT: [[ADD_I899:%.*]] = add i32 [[MUL_I894]],
>> [[SUM_11057]]
>> ; CHECK-T2-NEXT: [[ADD6_I900:%.*]] = add i32 [[ADD_I899]],
>> [[MUL5_I898]]
>> ; CHECK-T2-NEXT: [[ARRAYIDX_I885:%.*]] = getelementptr inbounds
>> i16, i16* [[PX_31055]], i32 3
>> -; CHECK-T2-NEXT: [[TMP11:%.*]] = load i16, i16*
>> [[ARRAYIDX_I885]], align 2
>> -; CHECK-T2-NEXT: [[TMP12:%.*]] = load i16, i16* [[ADD_PTR_I912]],
>> align 2
>> +; CHECK-T2-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX_I885]],
>> align 2
>> +; CHECK-T2-NEXT: [[TMP9:%.*]] = load i16, i16* [[ADD_PTR_I912]],
>> align 2
>> ; CHECK-T2-NEXT: [[ADD_PTR_I890]] = getelementptr inbounds i16,
>> i16* [[PX_31055]], i32 4
>> ; CHECK-T2-NEXT: [[ARRAYIDX_I879:%.*]] = getelementptr inbounds
>> i16, i16* [[PY_31056]], i32 -1
>> -; CHECK-T2-NEXT: [[TMP13:%.*]] = load i16, i16*
>> [[ARRAYIDX_I879]], align 2
>> -; CHECK-T2-NEXT: [[TMP14:%.*]] = load i16, i16* [[ADD_PTR_I906]],
>> align 2
>> +; CHECK-T2-NEXT: [[TMP10:%.*]] = load i16, i16*
>> [[ARRAYIDX_I879]], align 2
>> +; CHECK-T2-NEXT: [[TMP11:%.*]] = load i16, i16* [[ADD_PTR_I906]],
>> align 2
>> ; CHECK-T2-NEXT: [[ADD_PTR_I884]] = getelementptr inbounds i16,
>> i16* [[PY_31056]], i32 -4
>> -; CHECK-T2-NEXT: [[SHR_I870:%.*]] = sext i16 [[TMP12]] to i32
>> -; CHECK-T2-NEXT: [[SHR1_I871:%.*]] = sext i16 [[TMP13]] to i32
>> +; CHECK-T2-NEXT: [[SHR_I870:%.*]] = sext i16 [[TMP9]] to i32
>> +; CHECK-T2-NEXT: [[SHR1_I871:%.*]] = sext i16 [[TMP10]] to i32
>> ; CHECK-T2-NEXT: [[MUL_I872:%.*]] = mul nsw i32 [[SHR1_I871]],
>> [[SHR_I870]]
>> -; CHECK-T2-NEXT: [[SHR2_I873:%.*]] = sext i16 [[TMP11]] to i32
>> -; CHECK-T2-NEXT: [[SHR4_I875:%.*]] = sext i16 [[TMP14]] to i32
>> +; CHECK-T2-NEXT: [[SHR2_I873:%.*]] = sext i16 [[TMP8]] to i32
>> +; CHECK-T2-NEXT: [[SHR4_I875:%.*]] = sext i16 [[TMP11]] to i32
>> ; CHECK-T2-NEXT: [[MUL5_I876:%.*]] = mul nsw i32 [[SHR4_I875]],
>> [[SHR2_I873]]
>> ; CHECK-T2-NEXT: [[ADD_I877:%.*]] = add i32 [[ADD6_I900]],
>> [[MUL_I872]]
>> ; CHECK-T2-NEXT: [[ADD6_I878]] = add i32 [[ADD_I877]],
>> [[MUL5_I876]]
>> @@ -317,11 +311,11 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T2-NEXT: [[PY_41064:%.*]] = phi i16* [
>> [[INCDEC_PTR39:%.*]], [[WHILE_BODY36]] ], [ [[ADD_PTR32]],
>> [[WHILE_BODY36_PREHEADER]] ]
>> ; CHECK-T2-NEXT: [[PX_41063:%.*]] = phi i16* [
>> [[INCDEC_PTR37:%.*]], [[WHILE_BODY36]] ], [ [[PX_3_LCSSA]],
>> [[WHILE_BODY36_PREHEADER]] ]
>> ; CHECK-T2-NEXT: [[INCDEC_PTR37]] = getelementptr inbounds i16,
>> i16* [[PX_41063]], i32 1
>> -; CHECK-T2-NEXT: [[TMP15:%.*]] = load i16, i16* [[PX_41063]],
>> align 2
>> -; CHECK-T2-NEXT: [[CONV38:%.*]] = sext i16 [[TMP15]] to i32
>> +; CHECK-T2-NEXT: [[TMP12:%.*]] = load i16, i16* [[PX_41063]],
>> align 2
>> +; CHECK-T2-NEXT: [[CONV38:%.*]] = sext i16 [[TMP12]] to i32
>> ; CHECK-T2-NEXT: [[INCDEC_PTR39]] = getelementptr inbounds i16,
>> i16* [[PY_41064]], i32 -1
>> -; CHECK-T2-NEXT: [[TMP16:%.*]] = load i16, i16* [[PY_41064]],
>> align 2
>> -; CHECK-T2-NEXT: [[CONV40:%.*]] = sext i16 [[TMP16]] to i32
>> +; CHECK-T2-NEXT: [[TMP13:%.*]] = load i16, i16* [[PY_41064]],
>> align 2
>> +; CHECK-T2-NEXT: [[CONV40:%.*]] = sext i16 [[TMP13]] to i32
>> ; CHECK-T2-NEXT: [[MUL_I863:%.*]] = mul nsw i32 [[CONV40]],
>> [[CONV38]]
>> ; CHECK-T2-NEXT: [[SHR3_I864:%.*]] = ashr i32 [[CONV38]], 16
>> ; CHECK-T2-NEXT: [[SHR4_I865:%.*]] = ashr i32 [[CONV40]], 16
>> @@ -336,8 +330,8 @@ define dso_local arm_aapcscc void
>> @arm_conv_fast_q15(i16* %pSrcA, i32 %srcALen,
>> ; CHECK-T2-NEXT: br label [[WHILE_END43]]
>> ; CHECK-T2: while.end43:
>> ; CHECK-T2-NEXT: [[SUM_2_LCSSA:%.*]] = phi i32 [
>> [[SUM_1_LCSSA]], [[WHILE_END31]] ], [ [[ADD6_I868_LCSSA]],
>> [[WHILE_END43_LOOPEXIT]] ]
>> -; CHECK-T2-NEXT: [[TMP17:%.*]] = lshr i32 [[SUM_2_LCSSA]], 15
>> -; CHECK-T2-NEXT: [[CONV45:%.*]] = trunc i32 [[TMP17]] to i16
>> +; CHECK-T2-NEXT: [[TMP14:%.*]] = lshr i32 [[SUM_2_LCSSA]], 15
>> +; CHECK-T2-NEXT: [[CONV45:%.*]] = trunc i32 [[TMP14]] to i16
>> ; CHECK-T2-NEXT: [[INCDEC_PTR46]] = getelementptr inbounds i16,
>> i16* [[POUT_11069]], i32 1
>> ; CHECK-T2-NEXT: store i16 [[CONV45]], i16* [[POUT_11069]], align 2
>> ; CHECK-T2-NEXT: [[SUB47:%.*]] = add i32 [[COUNT_11072]], -1
>>
>> diff --git
>> a/llvm/test/Transforms/IndVarSimplify/do-recompute-if-cheap.ll
>> b/llvm/test/Transforms/IndVarSimplify/dont-recompute.ll
>> similarity index 91%
>> rename from llvm/test/Transforms/IndVarSimplify/do-recompute-if-cheap.ll
>> rename to llvm/test/Transforms/IndVarSimplify/dont-recompute.ll
>> index 869f55e1d6dc..91abc06529a1 100644
>> --- a/llvm/test/Transforms/IndVarSimplify/do-recompute-if-cheap.ll
>> +++ b/llvm/test/Transforms/IndVarSimplify/dont-recompute.ll
>> @@ -36,8 +36,8 @@ define void @test(i32 %m) nounwind uwtable {
>> ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 186
>> ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label
>> [[FOR_BODY]]
>> ; CHECK: for.end:
>> -; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[M]], 186
>> -; CHECK-NEXT: tail call void @func(i32 [[TMP0]])
>> +; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ]
>> +; CHECK-NEXT: tail call void @func(i32 [[ADD_LCSSA]])
>> ; CHECK-NEXT: ret void
>> ;
>> entry:
>> @@ -70,8 +70,8 @@ define i32 @test2(i32 %m) nounwind uwtable {
>> ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 186
>> ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label
>> [[FOR_BODY]]
>> ; CHECK: for.end:
>> -; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[M]], 186
>> -; CHECK-NEXT: ret i32 [[TMP0]]
>> +; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ]
>> +; CHECK-NEXT: ret i32 [[ADD_LCSSA]]
>> ;
>> entry:
>> br label %for.body
>> @@ -102,8 +102,8 @@ define void @test3(i32 %m) nounwind uwtable {
>> ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 186
>> ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label
>> [[FOR_BODY]]
>> ; CHECK: for.end:
>> -; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[M]], 186
>> -; CHECK-NEXT: tail call void @func(i32 [[TMP0]])
>> +; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ]
>> +; CHECK-NEXT: tail call void @func(i32 [[ADD_LCSSA]])
>> ; CHECK-NEXT: ret void
>> ;
>> entry:
>> @@ -142,8 +142,8 @@ define void @test4(i32 %m) nounwind uwtable {
>> ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 186
>> ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label
>> [[FOR_BODY]]
>> ; CHECK: for.end:
>> -; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[M]], 186
>> -; CHECK-NEXT: [[SOFT_USE:%.*]] = add i32 [[TMP0]], 123
>> +; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ]
>> +; CHECK-NEXT: [[SOFT_USE:%.*]] = add i32 [[ADD_LCSSA]], 123
>> ; CHECK-NEXT: tail call void @func(i32 [[SOFT_USE]])
>> ; CHECK-NEXT: ret void
>> ;
>> @@ -179,8 +179,8 @@ define void @test5(i32 %m) nounwind uwtable {
>> ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 186
>> ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label
>> [[FOR_BODY]]
>> ; CHECK: for.end:
>> -; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[M]], 186
>> -; CHECK-NEXT: tail call void @func(i32 [[TMP0]])
>> +; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ]
>> +; CHECK-NEXT: tail call void @func(i32 [[ADD_LCSSA]])
>> ; CHECK-NEXT: ret void
>> ;
>> entry:
>> @@ -216,8 +216,8 @@ define void @test6(i32 %m, i32* %p) nounwind
>> uwtable {
>> ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 186
>> ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label
>> [[FOR_BODY]]
>> ; CHECK: for.end:
>> -; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[M]], 186
>> -; CHECK-NEXT: tail call void @func(i32 [[TMP0]])
>> +; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ]
>> +; CHECK-NEXT: tail call void @func(i32 [[ADD_LCSSA]])
>> ; CHECK-NEXT: ret void
>> ;
>> entry:
>>
>> diff --git a/llvm/test/Transforms/IndVarSimplify/elim-extend.ll
>> b/llvm/test/Transforms/IndVarSimplify/elim-extend.ll
>> index 3387cfa9bbbd..14c9c99903ce 100644
>> --- a/llvm/test/Transforms/IndVarSimplify/elim-extend.ll
>> +++ b/llvm/test/Transforms/IndVarSimplify/elim-extend.ll
>> @@ -143,7 +143,8 @@ define void @nestedIV(i8* %address, i32 %limit)
>> nounwind {
>> ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64
>> [[INDVARS_IV_NEXT]], [[TMP0]]
>> ; CHECK-NEXT: br i1 [[EXITCOND]], label [[INNERLOOP]], label
>> [[INNEREXIT:%.*]]
>> ; CHECK: innerexit:
>> -; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP0]] to i32
>> +; CHECK-NEXT: [[INNERCOUNT_LCSSA_WIDE:%.*]] = phi i64 [
>> [[INDVARS_IV_NEXT]], [[INNERLOOP]] ]
>> +; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[INNERCOUNT_LCSSA_WIDE]]
>> to i32
>> ; CHECK-NEXT: br label [[OUTERMERGE]]
>> ; CHECK: outermerge:
>> ; CHECK-NEXT: [[INNERCOUNT_MERGE]] = phi i32 [ [[TMP4]],
>> [[INNEREXIT]] ], [ [[INNERCOUNT]], [[INNERPREHEADER]] ]
>>
>> diff --git
>> a/llvm/test/Transforms/IndVarSimplify/lrev-existing-umin.ll
>> b/llvm/test/Transforms/IndVarSimplify/lrev-existing-umin.ll
>> index 5fc2b3068f19..6ef7a5ce9e26 100644
>> --- a/llvm/test/Transforms/IndVarSimplify/lrev-existing-umin.ll
>> +++ b/llvm/test/Transforms/IndVarSimplify/lrev-existing-umin.ll
>> @@ -26,7 +26,8 @@ define void @f(i32 %length.i.88, i32 %length.i, i8*
>> %tmp12, i32 %tmp10, i8* %tmp
>> ; CHECK-NEXT: [[TMP23:%.*]] = icmp slt i32 [[TMP22]], [[TMP14]]
>> ; CHECK-NEXT: br i1 [[TMP23]], label [[NOT_ZERO11]], label
>> [[MAIN_EXIT_SELECTOR:%.*]]
>> ; CHECK: main.exit.selector:
>> -; CHECK-NEXT: [[TMP24:%.*]] = icmp slt i32 [[TMP14]], [[LENGTH_I]]
>> +; CHECK-NEXT: [[TMP22_LCSSA:%.*]] = phi i32 [ [[TMP22]],
>> [[NOT_ZERO11]] ]
>> +; CHECK-NEXT: [[TMP24:%.*]] = icmp slt i32 [[TMP22_LCSSA]],
>> [[LENGTH_I]]
>> ; CHECK-NEXT: br i1 [[TMP24]], label [[NOT_ZERO11_POSTLOOP]],
>> label [[LEAVE:%.*]]
>> ; CHECK: leave:
>> ; CHECK-NEXT: ret void
>>
>> diff --git a/llvm/test/Transforms/IndVarSimplify/pr28705.ll
>> b/llvm/test/Transforms/IndVarSimplify/pr28705.ll
>> index b431a28a4888..a6fed805dc65 100644
>> --- a/llvm/test/Transforms/IndVarSimplify/pr28705.ll
>> +++ b/llvm/test/Transforms/IndVarSimplify/pr28705.ll
>> @@ -16,14 +16,14 @@ define void @foo(i32 %sub.ptr.div.i, i8*
>> %ref.i1174) local_unnamed_addr {
>> ; CHECK: for.body650.lr.ph:
>> ; CHECK-NEXT: br label [[FOR_BODY650:%.*]]
>> ; CHECK: loopexit:
>> -; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[DOTSROA_SPECULATED]], 1
>> +; CHECK-NEXT: [[INC_I_I_LCSSA:%.*]] = phi i32 [ [[INC_I_I:%.*]],
>> [[FOR_BODY650]] ]
>> ; CHECK-NEXT: br label [[XZ_EXIT]]
>> ; CHECK: XZ.exit:
>> -; CHECK-NEXT: [[DB_SROA_9_0_LCSSA:%.*]] = phi i32 [ 1,
>> [[ENTRY:%.*]] ], [ [[TMP0]], [[LOOPEXIT:%.*]] ]
>> +; CHECK-NEXT: [[DB_SROA_9_0_LCSSA:%.*]] = phi i32 [ 1,
>> [[ENTRY:%.*]] ], [ [[INC_I_I_LCSSA]], [[LOOPEXIT:%.*]] ]
>> ; CHECK-NEXT: br label [[END:%.*]]
>> ; CHECK: for.body650:
>> ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[FOR_BODY650_LR_PH]] ],
>> [ [[INC655:%.*]], [[FOR_BODY650]] ]
>> -; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 1, [[FOR_BODY650_LR_PH]] ],
>> [ [[INC_I_I:%.*]], [[FOR_BODY650]] ]
>> +; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 1, [[FOR_BODY650_LR_PH]] ],
>> [ [[INC_I_I]], [[FOR_BODY650]] ]
>> ; CHECK-NEXT: [[ARRAYIDX_I_I1105:%.*]] = getelementptr inbounds
>> i8, i8* [[REF_I1174:%.*]], i32 [[IV2]]
>> ; CHECK-NEXT: store i8 7, i8* [[ARRAYIDX_I_I1105]], align 1
>> ; CHECK-NEXT: [[INC_I_I]] = add nuw nsw i32 [[IV2]], 1
>>
>> diff --git a/llvm/test/Transforms/IndVarSimplify/pr39673.ll
>> b/llvm/test/Transforms/IndVarSimplify/pr39673.ll
>> index 4ae9f4532d50..7fb90a90071a 100644
>> --- a/llvm/test/Transforms/IndVarSimplify/pr39673.ll
>> +++ b/llvm/test/Transforms/IndVarSimplify/pr39673.ll
>> @@ -72,8 +72,8 @@ define i16 @dom_argument(i16 %arg1, i16 %arg2) {
>> ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i16 [[L2_ADD]], 2
>> ; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP2]], label
>> [[LOOP2_END:%.*]]
>> ; CHECK: loop2.end:
>> -; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[ARG2]], 2
>> -; CHECK-NEXT: ret i16 [[TMP0]]
>> +; CHECK-NEXT: [[K2_ADD_LCSSA:%.*]] = phi i16 [ [[K2_ADD]],
>> [[LOOP2]] ]
>> +; CHECK-NEXT: ret i16 [[K2_ADD_LCSSA]]
>> ;
>> entry:
>> br label %loop1
>> @@ -121,8 +121,8 @@ define i16 @dummy_phi_outside_loop(i16 %arg) {
>> ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i16 [[L2_ADD]], 2
>> ; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP2]], label
>> [[LOOP2_END:%.*]]
>> ; CHECK: loop2.end:
>> -; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[DUMMY]], 2
>> -; CHECK-NEXT: ret i16 [[TMP0]]
>> +; CHECK-NEXT: [[K2_ADD_LCSSA:%.*]] = phi i16 [ [[K2_ADD]],
>> [[LOOP2]] ]
>> +; CHECK-NEXT: ret i16 [[K2_ADD_LCSSA]]
>> ;
>> entry:
>> br label %loop2.preheader
>> @@ -166,8 +166,8 @@ define i16 @neg_loop_carried(i16 %arg) {
>> ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i16 [[L2_ADD]], 2
>> ; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP2]], label
>> [[LOOP2_END:%.*]]
>> ; CHECK: loop2.end:
>> -; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[TMP0]], 2
>> -; CHECK-NEXT: ret i16 [[TMP1]]
>> +; CHECK-NEXT: [[K2_ADD_LCSSA:%.*]] = phi i16 [ [[K2_ADD]],
>> [[LOOP2]] ]
>> +; CHECK-NEXT: ret i16 [[K2_ADD_LCSSA]]
>> ;
>> entry:
>> br label %loop1
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at lists.llvm.org
>> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
More information about the llvm-commits
mailing list