[PATCH] D78907: [RISCV][NFC] Add tests for checking isnan patterns

[Sam Elliott via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG910ca0e43591: [RISCV][NFC] Add tests for checking isnan patterns (authored by lenary).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78907/new/

https://reviews.llvm.org/D78907

Files:
  llvm/test/CodeGen/RISCV/double-isnan.ll
  llvm/test/CodeGen/RISCV/float-isnan.ll


Index: llvm/test/CodeGen/RISCV/float-isnan.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/float-isnan.ll
@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV64IF %s
+
+define zeroext i1 @float_is_nan(float %a) nounwind {
+; RV32IF-LABEL: float_is_nan:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    feq.s a0, fa0, fa0
+; RV32IF-NEXT:    and a0, a0, a0
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: float_is_nan:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    feq.s a0, fa0, fa0
+; RV64IF-NEXT:    and a0, a0, a0
+; RV64IF-NEXT:    seqz a0, a0
+; RV64IF-NEXT:    ret
+  %1 = fcmp uno float %a, 0.000000e+00
+  ret i1 %1
+}
+
+define zeroext i1 @float_not_nan(float %a) nounwind {
+; RV32IF-LABEL: float_not_nan:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    feq.s a0, fa0, fa0
+; RV32IF-NEXT:    and a0, a0, a0
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: float_not_nan:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    feq.s a0, fa0, fa0
+; RV64IF-NEXT:    and a0, a0, a0
+; RV64IF-NEXT:    ret
+  %1 = fcmp ord float %a, 0.000000e+00
+  ret i1 %1
+}
Index: llvm/test/CodeGen/RISCV/double-isnan.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/double-isnan.ll
@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV32IFD %s
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV64IFD %s
+
+define zeroext i1 @double_is_nan(double %a) nounwind {
+; RV32IFD-LABEL: double_is_nan:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    feq.d a0, fa0, fa0
+; RV32IFD-NEXT:    and a0, a0, a0
+; RV32IFD-NEXT:    seqz a0, a0
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: double_is_nan:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    feq.d a0, fa0, fa0
+; RV64IFD-NEXT:    and a0, a0, a0
+; RV64IFD-NEXT:    seqz a0, a0
+; RV64IFD-NEXT:    ret
+  %1 = fcmp uno double %a, 0.000000e+00
+  ret i1 %1
+}
+
+define zeroext i1 @double_not_nan(double %a) nounwind {
+; RV32IFD-LABEL: double_not_nan:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    feq.d a0, fa0, fa0
+; RV32IFD-NEXT:    and a0, a0, a0
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: double_not_nan:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    feq.d a0, fa0, fa0
+; RV64IFD-NEXT:    and a0, a0, a0
+; RV64IFD-NEXT:    ret
+  %1 = fcmp ord double %a, 0.000000e+00
+  ret i1 %1
+}


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