[PATCH] D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added a comment.

In D78206#2014681 <https://reviews.llvm.org/D78206#2014681>, @samparker wrote:

> Sorry, I forgot about this. Thanks for that example, I now see how the VCTP can be Else predicated, but I obviously don't quite understand how VPT predication works! The code below is what is generated from the example and now I don't understand why the VSTR is Else predicated. Is it because it needs the same inverted predicate as the VCTP, coming from the VCMP, as well as being ANDed with the VCTP? My intuition wanted it to be Then predicated after the VCTP has already done an inversion.
>
>   vctp.32 r1
>   vpst
>   vldrwt.u32      q1, [r0]
>   vptee.s32       ge, q1, r2
>   vcmpt.s32       le, q1, r3
>   vctpe.32        r1
>   vstrwe.32       q0, [r0], #16
>   subs    r1, #4
>   le      lr, .LBB0_1
>   


The VPT Blocks pass changes the predicate to E when there is a VPNOT, so if it generated this code, there was a VPNOT between the VCTP/VCMP. This is why the last 2 instructions are else predicated.
The VSTR is else predicated as well because we want it to be executed only when the VCTP is. If it were then predicated, it wouldn't be the case - it would be executed even when both conditions evaluate to true (and the VCTP would be skipped).
(This is kind of related to D77798 <https://reviews.llvm.org/D77798>, which was a miscompilation issue that occured because we initially thought that we had to change the predicate back to a "then" after VPR is written to.)


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