[PATCH] D79096: [SelectionDAG] Unify scalarizeVectorLoad and VectorLegalizer::ExpandLoad

[LemonBoy via Phabricator via llvm-commits]

LemonBoy marked an inline comment as done.
LemonBoy added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6620
+      SDValue Elt =
+          DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask);
+      SDValue Scalar = DAG.getNode(ISD::TRUNCATE, SL, SrcEltVT, Elt);
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craig.topper wrote:
> LemonBoy wrote:
> > craig.topper wrote:
> > > Why do we need to AND before the TRUNCATE? Isn't the AND masking to the same number of bits as the truncate?
> > I found that sometimes the generated pattern would be something like `(anyext DstEltVT (truncate SrcEltVT (load LoadVT))` so when the optimizer kicks in and folds the `truncate` and `anyext` only the load remains.
> Why is that bad?
The extra bits are never masked away. If you bypass the `AND` and check out the generated code for `test2` in `X86/pr15267.ll` you can see the packed `4i1` is only shifted and never and-ed so the generated vector has garbage in upper bits.


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  https://reviews.llvm.org/D79096/new/

https://reviews.llvm.org/D79096