[PATCH] D79096: [SelectionDAG] Unify scalarizeVectorLoad and VectorLegalizer::ExpandLoad

[LemonBoy via Phabricator via llvm-commits]

LemonBoy marked 2 inline comments as done.
LemonBoy added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6604
+
+    // Load the whole vector including the padding bits. This avoids inserting
+    // extra bit masking that makes the codegen worse.
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craig.topper wrote:
> This comment doesn't completely make sense. The memory VT is still based on NumSrcBits so it isn't loading the padding bits.
Indeed, I only wanted to highlight the fact the extra bits aren't masked away when legalizing the odd-sized loads. I'll reword the comment.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6620
+      SDValue Elt =
+          DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask);
+      SDValue Scalar = DAG.getNode(ISD::TRUNCATE, SL, SrcEltVT, Elt);
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craig.topper wrote:
> Why do we need to AND before the TRUNCATE? Isn't the AND masking to the same number of bits as the truncate?
I found that sometimes the generated pattern would be something like `(anyext DstEltVT (truncate SrcEltVT (load LoadVT))` so when the optimizer kicks in and folds the `truncate` and `anyext` only the load remains.


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  https://reviews.llvm.org/D79096/new/

https://reviews.llvm.org/D79096