[PATCH] D78906: [RISCV] Add patterns for indirect float conversions

[Sam Elliott via Phabricator via llvm-commits]

lenary updated this revision to Diff 261193.
lenary added a comment.

Rebased onto rG09f6b9792bcdaa057d23caa62eb38265a3f1a668 <https://reviews.llvm.org/rG09f6b9792bcdaa057d23caa62eb38265a3f1a668> and changes in D78905 <https://reviews.llvm.org/D78905>.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78906/new/

https://reviews.llvm.org/D78906

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/test/CodeGen/RISCV/fp-convert-indirect.ll


Index: llvm/test/CodeGen/RISCV/fp-convert-indirect.ll
===================================================================
--- llvm/test/CodeGen/RISCV/fp-convert-indirect.ll
+++ llvm/test/CodeGen/RISCV/fp-convert-indirect.ll
@@ -28,8 +28,7 @@
 ;
 ; RV32IFD-LABEL: fcvt_s_w_via_d:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.w ft0, a0
-; RV32IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV32IFD-NEXT:    fcvt.s.w ft0, a0
 ; RV32IFD-NEXT:    fmv.x.w a0, ft0
 ; RV32IFD-NEXT:    ret
 ;
@@ -46,8 +45,7 @@
 ;
 ; RV64IFD-LABEL: fcvt_s_w_via_d:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.w ft0, a0
-; RV64IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV64IFD-NEXT:    fcvt.s.w ft0, a0
 ; RV64IFD-NEXT:    fmv.x.w a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = sitofp i32 %a to double
@@ -68,8 +66,7 @@
 ;
 ; RV32IFD-LABEL: fcvt_s_wu_via_d:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
-; RV32IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV32IFD-NEXT:    fcvt.s.wu ft0, a0
 ; RV32IFD-NEXT:    fmv.x.w a0, ft0
 ; RV32IFD-NEXT:    ret
 ;
@@ -87,8 +84,7 @@
 ;
 ; RV64IFD-LABEL: fcvt_s_wu_via_d:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
-; RV64IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV64IFD-NEXT:    fcvt.s.wu ft0, a0
 ; RV64IFD-NEXT:    fmv.x.w a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = uitofp i32 %a to double
Index: llvm/lib/Target/RISCV/RISCVInstrInfoF.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -392,6 +392,12 @@
 // [u]int->float. Match GCC and default to using dynamic rounding mode.
 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
+
+// [u]int->double->float
+def : Pat<(fpround (f64 (sint_to_fp GPR:$rs1))),
+          (FCVT_S_W GPR:$rs1, 0b111)>;
+def : Pat<(fpround (f64 (uint_to_fp GPR:$rs1))),
+          (FCVT_S_WU GPR:$rs1, 0b111)>;
 } // Predicates = [HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtF, IsRV64] in {
@@ -416,4 +422,11 @@
 def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>;
 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>;
+
+// [u]int->double->float
+def : Pat<(fpround (f64 (sint_to_fp (sext_inreg GPR:$rs1, i32)))),
+          (FCVT_S_W GPR:$rs1, 0b111)>;
+def : Pat<(fpround (f64 (uint_to_fp (zexti32 GPR:$rs1)))),
+          (FCVT_S_WU GPR:$rs1, 0b111)>;
+
 } // Predicates = [HasStdExtF, IsRV64]


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