[PATCH] D79141: [RISCV] Better Split Stack Pointer Adjustment for RVC

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:646
+  // adjustment.
+  if (CSI.size() > 0) {
+    const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
----------------
Could be early exit something like: if (CSI.size() == 0) return DoNotSplitSPAdjustment;


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:652
+    // use the smallest instructions available.
+    uint32_t OffsetAddressableLimit;
+    if (STI.hasStdExtC()) {
----------------
Could we extract a static function as getOffsetAddressableLimit(MF, StackAlign)? 


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:658
+      // On RV32C, the offset in these (the w variants, as the registers are
+      // word-sized) have a 7-bit limit.
+      //
----------------
Should be 8-bit limit for c.{l,s}wsp with isShiftedUInt<6, 2>(Imm)?


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:661
+      // On RV64C, the offset in these (the d variants, as the registers are
+      // double-sized) have an 8-bit limit, so we could use 512, but we also
+      // want to use c.addi16sp to adjust the stack pointer in the prolog and
----------------
Should be 9-bit limit for  c.{l,s}dsp with isShiftedUInt<6, 3>(Imm)?


================
Comment at: llvm/test/CodeGen/RISCV/split-sp-adjust.ll:138
+; RV32IC-NEXT:    c.swsp ra, 252(sp)
+; RV32IC-NEXT:    c.addi4spn a0, sp, 8
+; RV32IC-NEXT:    call use_pointer
----------------
The stack didn't split for rv32c because the stack size is 256 which is equal to the limit. Should we choose a slightly greater stack size for stack_split_rv32_c test case?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79141/new/

https://reviews.llvm.org/D79141