[PATCH] D79104: [X86] Update cost model for the cost of s/zextending from vXi1 to a vXi8/i16/i32 vector of less than 128 bits

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.
Herald added a subscriber: hiraditya.
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vXi1 vectors are legalized by promoting, but vXi8/i16/i32 vectors are legalized by widening. This results in these extends becoming truncates+sign/zext_extend_inreg. This is worse than the costs we were getting from the default TTI implementation.

We could probably lower the costs of these by improving the codegen to do the sign/zext_extend_inreg before the truncate. I think that would enable the use of packss/packus operations to do the truncation. Then we wouldn't need to insert an AND to make packus usable.


https://reviews.llvm.org/D79104

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/extend.ll
  llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll

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