[PATCH] D79003: [DAG] Add SimplifyDemandedVectorElts binop SimplifyMultipleUseDemandedBits handling

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: spatel, craig.topper, greened, efriedma.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.
RKSimon added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/mul_by_elt.ll:145
   ret <4 x float> %mul2
 }
 
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Not sure about this change - it strips the first shufflevector entirely losing the multiply by scalar, but instcombine would have done something similar anyhow:
```
define <4 x float> @splat0_before_fmul_fmul_constant(<4 x float> %a) {
  %1 = fmul <4 x float> %a, <float 3.000000e+00, float undef, float undef, float undef>
  %2 = fmul <4 x float> %1, <float 6.000000e+00, float undef, float undef, float undef>
  %mul2 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> zeroinitializer
  ret <4 x float> %mul2
}
```


For the supported binops (basic arithmetic, logicals + shifts), if we fail to simplify the demanded vector elts, then call SimplifyMultipleUseDemandedBits and try to peek through ops to remove unnecessary dependencies.

This helps with PR40502.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79003

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/mul_by_elt.ll
  llvm/test/CodeGen/X86/combine-pmuldq.ll
  llvm/test/CodeGen/X86/combine-sdiv.ll
  llvm/test/CodeGen/X86/oddsubvector.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-narrow-binop.ll

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