[PATCH] D78999: [SelectionDAGBuilder] Stop setting alignment to one for hidden sret values

[Alexander Richardson via Phabricator via llvm-commits]

arichardson created this revision.
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arichardson requested review of this revision.

We allocated a suitably aligned frame index so we know that all the values
have ABI alignment.
For MIPS this avoids using pair of lwl + lwr instructions instead of a
single lw. I found this when compiling CHERI pure capability code where
we can't use the lwl/lwr unaligned loads/stores and and were to falling
back to a byte load + shift + or sequence.

This should save a few instructions for MIPS and possibly other backends
that don't have fast unaligned loads/stores.
It also improves code generation for CodeGen/X86/pr34653.ll since it can
now use aligned loads.

Depends on D78998 <https://reviews.llvm.org/D78998>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78999

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/Mips/implicit-sret.ll
  llvm/test/CodeGen/X86/pr34653.ll

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