[PATCH] D72365: [MTE] Pin the tagged base pointer to one of the stack slots.

Mon Apr 27 14:01:16 PDT 2020

eugenis marked an inline comment as done.
eugenis added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp:256
+  //   instructions count.
+  // - Any other instruction may benefit from being pinned to offset 0.
+  LLVM_DEBUG(dbgs() << "AArch64StackTaggingPreRA::findFirstSlotCandidate\n");
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rankov wrote:
> Size of the slot might be important because of the range of addg. It can only reach 2^6 tag granules (64 * 16B) from base register. If you select a large slot it will reduce the number of slots that can be reached with addg and will result in additional add instructions.
> 
> Also, it might be beneficial to sort smaller slots near the SP.
I've tried sorting by size and/or access density (size / number of references) in D72366, but could not show any significant improvement. There are conflicting requirements there between minimizing the average ld/st immediate offset, maximizing the number of references to the object with tag 0 & offset 0, and keeping the objects that are untagged at the same time together (for STG merging).

I may return to this problem at some later time.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72365/new/

https://reviews.llvm.org/D72365