[PATCH] D78930: [MLIR] Give AffineStoreOp and AffineLoadOp Memory SideEffects.

[River Riddle via Phabricator via llvm-commits]

rriddle accepted this revision.
rriddle added inline comments.


================
Comment at: mlir/include/mlir/Dialect/Affine/IR/AffineOps.td:688
+
+def AffineLoadOp : Affine_Op<"load", []> {
+  let summary = "affine load operation";
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Can you keep this file sorted alphabetically?


Repository:
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  https://reviews.llvm.org/D78930/new/

https://reviews.llvm.org/D78930