[PATCH] D78889: [VE] Update branch instructions

[Simon Moll via Phabricator via llvm-commits]

simoll added a comment.

LGTM. Again, only some minor remarks.



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Comment at: llvm/lib/Target/VE/VEInstrInfo.cpp:28
 
-#define DEBUG_TYPE "ve"
+#define DEBUG_TYPE "ve-instr-info"
 
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unrelated change


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Comment at: llvm/lib/Target/VE/VEInstrInfo.cpp:206
     assert(!FBB && "Unconditional branch with multiple successors!");
-    BuildMI(&MBB, DL, get(VE::BCRLa))
-        .addMBB(TBB);
+    BuildMI(&MBB, DL, get(VE::BRCFLa_t)).addMBB(TBB);
     return 1;
----------------
Formatting. Please put the `addMBB` on the next line to follow the style of the code.


================
Comment at: llvm/lib/Target/VE/VEInstrInfo.cpp:253
 
-  BuildMI(&MBB, DL, get(VE::BCRLa))
-      .addMBB(FBB);
+  BuildMI(&MBB, DL, get(VE::BRCFLa_t)).addMBB(FBB);
   return 2;
----------------
same


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Comment at: llvm/lib/Target/VE/VEInstrInfo.td:1131
+def CALLr : RM<0x08, (outs), (ins I64:$sz, variable_ops),
+               "bsic %s10, (, $sz)", [(call i64:$sz)]>;
 
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In the tests below `%lr` has turned into `%s10` . I suppose you could replace the asm string `bsic %s10` here with `bsic %lr` to prevent this (at least for this pattern).


Repository:
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