[PATCH] D78800: [AMDGPU] Skip generating cache invalidating instructions on AMDPAL

[Tony Tye via Phabricator via llvm-commits]

t-tye added a comment.

@nhaehnle my thinking was that the Vulkan memory model could be semantically represented in the LLVM IR by adding new memory orderings to make the distinction of the effective two sets of memory that the Vulkam memory model introduces. There needs to be memory orderings that only relates to the subset that Vulkan is requiring to be coherent. However, I have not followed the Vulkan memory model specification recently so not sure if it is still the same as when I was looking at it. What are your thoughts?


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  https://reviews.llvm.org/D78800/new/

https://reviews.llvm.org/D78800