[compiler-rt] 25e2261 - [XRay] Change ARM/AArch64/powerpc64le to use version 2 sled (PC-relative address)
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 24 08:40:21 PDT 2020
Author: Fangrui Song
Date: 2020-04-24T08:35:43-07:00
New Revision: 25e22613dfdb4083056e8a951aeb246bea4019f3
URL: https://github.com/llvm/llvm-project/commit/25e22613dfdb4083056e8a951aeb246bea4019f3
DIFF: https://github.com/llvm/llvm-project/commit/25e22613dfdb4083056e8a951aeb246bea4019f3.diff
LOG: [XRay] Change ARM/AArch64/powerpc64le to use version 2 sled (PC-relative address)
Follow-up of D78082 (x86-64).
This change avoids dynamic relocations in `xray_instr_map` for ARM/AArch64/powerpc64le.
MIPS64 cannot use 64-bit PC-relative addresses because R_MIPS_PC64 is not defined.
Because MIPS32 shares the same code, for simplicity, we don't use PC-relative addresses for MIPS32 as well.
Tested on AArch64 Linux and ppc64le Linux.
Reviewed By: ianlevesque
Differential Revision: https://reviews.llvm.org/D78590
Added:
Modified:
compiler-rt/lib/xray/xray_AArch64.cpp
compiler-rt/lib/xray/xray_arm.cpp
compiler-rt/lib/xray/xray_interface_internal.h
compiler-rt/lib/xray/xray_powerpc64.cpp
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/ARM/ARMMCInstLower.cpp
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/test/CodeGen/AArch64/xray-tail-call-sled.ll
llvm/test/CodeGen/ARM/xray-tail-call-sled.ll
llvm/test/CodeGen/PowerPC/xray-attribute-instrumentation.ll
llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll
Removed:
################################################################################
diff --git a/compiler-rt/lib/xray/xray_AArch64.cpp b/compiler-rt/lib/xray/xray_AArch64.cpp
index 081941b70375..00105d30b4db 100644
--- a/compiler-rt/lib/xray/xray_AArch64.cpp
+++ b/compiler-rt/lib/xray/xray_AArch64.cpp
@@ -61,7 +61,7 @@ inline static bool patchSled(const bool Enable, const uint32_t FuncId,
// When |Enable|==false, we set back the first instruction in the sled to be
// B #32
- uint32_t *FirstAddress = reinterpret_cast<uint32_t *>(Sled.Address);
+ uint32_t *FirstAddress = reinterpret_cast<uint32_t *>(Sled.address());
uint32_t *CurAddress = FirstAddress + 1;
if (Enable) {
*CurAddress = uint32_t(PatchOpcodes::PO_LdrW0_12);
diff --git a/compiler-rt/lib/xray/xray_arm.cpp b/compiler-rt/lib/xray/xray_arm.cpp
index 9ad8065eb886..e1818555906c 100644
--- a/compiler-rt/lib/xray/xray_arm.cpp
+++ b/compiler-rt/lib/xray/xray_arm.cpp
@@ -102,7 +102,7 @@ inline static bool patchSled(const bool Enable, const uint32_t FuncId,
// When |Enable|==false, we set back the first instruction in the sled to be
// B #20
- uint32_t *FirstAddress = reinterpret_cast<uint32_t *>(Sled.Address);
+ uint32_t *FirstAddress = reinterpret_cast<uint32_t *>(Sled.address());
uint32_t *CurAddress = FirstAddress + 1;
if (Enable) {
CurAddress =
diff --git a/compiler-rt/lib/xray/xray_interface_internal.h b/compiler-rt/lib/xray/xray_interface_internal.h
index 2a185973d9f7..cdd1b9cbe2d6 100644
--- a/compiler-rt/lib/xray/xray_interface_internal.h
+++ b/compiler-rt/lib/xray/xray_interface_internal.h
@@ -30,16 +30,10 @@ struct XRaySledEntry {
unsigned char Version;
unsigned char Padding[13]; // Need 32 bytes
uint64_t address() const {
-#ifndef __x86_64__
- // R_MIPS_PC64 does not exist. Use absolute address even for version 2.
- return Address;
-#else
- // TODO Eventually all targets but MIPS64 should take this branch.
if (Version < 2)
return Address;
// The target address is relative to the location of the Address variable.
return reinterpret_cast<uint64_t>(&Address) + Address;
-#endif
}
#elif SANITIZER_WORDSIZE == 32
uint32_t Address;
@@ -48,7 +42,12 @@ struct XRaySledEntry {
unsigned char AlwaysInstrument;
unsigned char Version;
unsigned char Padding[5]; // Need 16 bytes
- uint32_t address() const { return Address; }
+ uint32_t address() const {
+ if (Version < 2)
+ return Address;
+ // The target address is relative to the location of the Address variable.
+ return reinterpret_cast<uint32_t>(&Address) + Address;
+ }
#else
#error "Unsupported word size."
#endif
diff --git a/compiler-rt/lib/xray/xray_powerpc64.cpp b/compiler-rt/lib/xray/xray_powerpc64.cpp
index 067488b5c900..c3553d848313 100644
--- a/compiler-rt/lib/xray/xray_powerpc64.cpp
+++ b/compiler-rt/lib/xray/xray_powerpc64.cpp
@@ -52,7 +52,7 @@ namespace __xray {
bool patchFunctionEntry(const bool Enable, uint32_t FuncId,
const XRaySledEntry &Sled,
void (*Trampoline)()) XRAY_NEVER_INSTRUMENT {
- const uint64_t Address = Sled.Address;
+ const uint64_t Address = Sled.address();
if (Enable) {
// lis 0, FuncId[16..32]
// li 0, FuncId[0..15]
@@ -70,7 +70,7 @@ bool patchFunctionEntry(const bool Enable, uint32_t FuncId,
bool patchFunctionExit(const bool Enable, uint32_t FuncId,
const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
- const uint64_t Address = Sled.Address;
+ const uint64_t Address = Sled.address();
if (Enable) {
// lis 0, FuncId[16..32]
// li 0, FuncId[0..15]
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 9c9cafe029dc..7b9bcb636861 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -3201,8 +3201,9 @@ void AsmPrinter::emitXRayTable() {
MCSection *InstMap = nullptr;
MCSection *FnSledIndex = nullptr;
const Triple &TT = TM.getTargetTriple();
- // Version 2 uses a PC-relative address on all supported targets.
- bool PCRel = TT.isX86();
+ // Use PC-relative addresses on all targets except MIPS (MIPS64 cannot use
+ // PC-relative addresses because R_MIPS_PC64 does not exist).
+ bool PCRel = !TT.isMIPS();
if (TT.isOSBinFormatELF()) {
auto LinkedToSym = cast<MCSymbolELF>(CurrentFnSym);
auto Flags = ELF::SHF_ALLOC | ELF::SHF_LINK_ORDER;
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index f1978081a0b0..c450558a07ce 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -313,7 +313,7 @@ void AArch64AsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
OutStreamer->emitLabel(Target);
- recordSled(CurSled, MI, Kind);
+ recordSled(CurSled, MI, Kind, 2);
}
void AArch64AsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
diff --git a/llvm/lib/Target/ARM/ARMMCInstLower.cpp b/llvm/lib/Target/ARM/ARMMCInstLower.cpp
index f8f65225b1f7..f893faa4cf97 100644
--- a/llvm/lib/Target/ARM/ARMMCInstLower.cpp
+++ b/llvm/lib/Target/ARM/ARMMCInstLower.cpp
@@ -210,7 +210,7 @@ void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
emitNops(NoopsInSledCount);
OutStreamer->emitLabel(Target);
- recordSled(CurSled, MI, Kind);
+ recordSled(CurSled, MI, Kind, 2);
}
void ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index bc2d12fa0f1a..d4fd0fb77a05 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1181,7 +1181,7 @@ void PPCLinuxAsmPrinter::emitInstruction(const MachineInstr *MI) {
OutContext)));
EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTLR8).addReg(PPC::X0));
OutStreamer->emitLabel(EndOfSled);
- recordSled(BeginOfSled, *MI, SledKind::FUNCTION_ENTER);
+ recordSled(BeginOfSled, *MI, SledKind::FUNCTION_ENTER, 2);
break;
}
case TargetOpcode::PATCHABLE_RET: {
@@ -1269,7 +1269,7 @@ void PPCLinuxAsmPrinter::emitInstruction(const MachineInstr *MI) {
EmitToStreamer(*OutStreamer, RetInst);
if (IsConditional)
OutStreamer->emitLabel(FallthroughLabel);
- recordSled(BeginOfSled, *MI, SledKind::FUNCTION_EXIT);
+ recordSled(BeginOfSled, *MI, SledKind::FUNCTION_EXIT, 2);
break;
}
case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
diff --git a/llvm/test/CodeGen/AArch64/xray-tail-call-sled.ll b/llvm/test/CodeGen/AArch64/xray-tail-call-sled.ll
index f966362b805e..b6f7a4edbed5 100644
--- a/llvm/test/CodeGen/AArch64/xray-tail-call-sled.ll
+++ b/llvm/test/CodeGen/AArch64/xray-tail-call-sled.ll
@@ -28,9 +28,11 @@ define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-alway
; CHECK-NEXT: ret
}
; CHECK-LABEL: xray_instr_map
-; CHECK-LABEL: Lxray_sleds_start0:
-; CHECK: .xword .Lxray_sled_0
-; CHECK: .xword .Lxray_sled_1
+; CHECK-LABEL: .Lxray_sleds_start0:
+; CHECK-NEXT: .Ltmp2:
+; CHECK: .xword .Lxray_sled_0-.Ltmp2
+; CHECK: .Ltmp3:
+; CHECK-NEXT: .xword .Lxray_sled_1-.Ltmp3
; CHECK-LABEL: Lxray_sleds_end0:
; CHECK-LABEL: xray_fn_idx
; CHECK: .xword .Lxray_sleds_start0
@@ -47,7 +49,7 @@ define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-alway
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
-; CHECK-LABEL: .Ltmp2:
+; CHECK-LABEL: .Ltmp4:
; CHECK: .p2align 2
; CHECK-LABEL: Lxray_sled_3:
; CHECK-NEXT: b #32
@@ -58,7 +60,7 @@ define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-alway
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
-; CHECK-LABEL: .Ltmp3:
+; CHECK-LABEL: .Ltmp5:
%retval = tail call i32 @callee()
; CHECK: b callee
ret i32 %retval
diff --git a/llvm/test/CodeGen/ARM/xray-tail-call-sled.ll b/llvm/test/CodeGen/ARM/xray-tail-call-sled.ll
index f6769c04603a..2d3af5595f13 100644
--- a/llvm/test/CodeGen/ARM/xray-tail-call-sled.ll
+++ b/llvm/test/CodeGen/ARM/xray-tail-call-sled.ll
@@ -37,7 +37,7 @@ define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-alway
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
-; CHECK-LABEL: Ltmp2:
+; CHECK-LABEL: Ltmp4:
; CHECK: .p2align 2
; CHECK-LABEL: Lxray_sled_3:
; CHECK-NEXT: b #20
@@ -47,7 +47,7 @@ define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-alway
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
-; CHECK-LABEL: Ltmp3:
+; CHECK-LABEL: Ltmp5:
%retval = tail call i32 @callee()
; CHECK: b {{.*}}callee
ret i32 %retval
diff --git a/llvm/test/CodeGen/PowerPC/xray-attribute-instrumentation.ll b/llvm/test/CodeGen/PowerPC/xray-attribute-instrumentation.ll
index 91beadca97ac..63c34be51ec3 100644
--- a/llvm/test/CodeGen/PowerPC/xray-attribute-instrumentation.ll
+++ b/llvm/test/CodeGen/PowerPC/xray-attribute-instrumentation.ll
@@ -22,19 +22,21 @@ define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always"
; CHECK-NEXT: nop
; CHECK-NEXT: mtlr 0
}
-; CHECK-LABEL: xray_instr_map,"awo", at progbits,foo{{$}}
+; CHECK-LABEL: xray_instr_map,"ao", at progbits,foo{{$}}
; CHECK: .Lxray_sleds_start0:
-; CHECK-NEXT: .quad .Ltmp0
+; CHECK-NEXT: .Ltmp3:
+; CHECK-NEXT: .quad .Ltmp0-.Ltmp3
; CHECK-NEXT: .quad foo
; CHECK-NEXT: .byte 0x00
; CHECK-NEXT: .byte 0x01
-; CHECK-NEXT: .byte 0x00
+; CHECK-NEXT: .byte 0x02
; CHECK-NEXT: .space 13
-; CHECK-NEXT: .quad .Ltmp2
+; CHECK-NEXT: .Ltmp4:
+; CHECK-NEXT: .quad .Ltmp2-.Ltmp4
; CHECK-NEXT: .quad foo
; CHECK-NEXT: .byte 0x01
; CHECK-NEXT: .byte 0x01
-; CHECK-NEXT: .byte 0x00
+; CHECK-NEXT: .byte 0x02
; CHECK-NEXT: .space 13
; CHECK-NEXT: .Lxray_sleds_end0:
; CHECK-LABEL: xray_fn_idx,"awo", at progbits,foo{{$}}
diff --git a/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll b/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll
index 90a928a90d07..e071e8ae4013 100644
--- a/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll
+++ b/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll
@@ -22,18 +22,18 @@ define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-alway
}
define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
-; CHECK-LABEL: .Ltmp3:
-; CHECK: b .Ltmp4
+; CHECK-LABEL: .Ltmp5:
+; CHECK-NEXT: b .Ltmp6
; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1)
; CHECK-NEXT: mflr 0
; CHECK-NEXT: bl __xray_FunctionEntry
; CHECK-NEXT: nop
; CHECK-NEXT: mtlr 0
-; CHECK-LABEL: .Ltmp4:
+; CHECK-LABEL: .Ltmp6:
%retval = tail call i32 @callee()
ret i32 %retval
-; CHECK-LABEL: .Ltmp5:
+; CHECK-LABEL: .Ltmp7:
; CHECK: blr
; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1)
More information about the llvm-commits
mailing list