[PATCH] D75344: [PowerPC] Exploit VSX neg, abs and nabs instruction for f32

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:1025
+// in v2.06. Reduce extra complexity to generate FNMSUBS in POWER7 targets.
+let AddedComplexity = 1 in
+def : Pat<(f32 (fneg f32:$S)),
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Can we use the pred that checking the pwr7 cpu type instead of harding code the complexity ? And the comment here is also unclear to me. You want to have fneg in P7 so that, it could be combined into fnmsub. We cannot combine fmsub + xsnegdp to fnmsub, is it right ?  General speaking, still emit the fneg for P7 makes sense to me.


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https://reviews.llvm.org/D75344