[PATCH] D78569: [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7670
+                     Mask, Op.getOperand(0), Op.getOperand(1));
+}
+
----------------
efriedma wrote:
> If we're going to support these operations, we might as well just add isel patterns; that's what we've been doing for other arithmetic operations.
Just to provide a bit of context to this approach:

For unpredicated ISD nodes for which there is no predicated instruction, the predicate needs to be generated. For scalable vectors this will be a `ptrue all`, but for fixed-width vectors may take some other predicate such as VL8 for fixed `8` elements.

Rather than creating new predicated AArch64 ISD nodes for each operation such as `AArch64ISD::UDIV_PRED`, the idea is to reuse the intrinsic layer we already added to support the ACLE - which are predicated and for which we already have the patterns - and map directly onto those.

By doing the expansion in ISelLowering, the patterns stay simple and we can generalise `getPtrue` method so that it generates the right predicate for any scalable/fixed vector size as done in D71760 avoiding the need to write multiple patterns for different vector lengths.

This patch was meant as the proof of concept of that idea (as discussed in the sync-up call of Apr 2). 


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Comment at: llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll:28
+; CHECK: ptrue p0.s
+; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT: sdiv z1.s, p0/m, z1.s, z3.s
----------------
This test should use CHECK-DAG instead of CHECK-NEXT, as the sdiv instructions are independent. (same for some of the other tests)


Repository:
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  https://reviews.llvm.org/D78569/new/

https://reviews.llvm.org/D78569