[PATCH] D78553: [AMDGPU] Simplify definition of VReg and AReg classes. NFC.

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 21 11:20:52 PDT 2020


rampitec accepted this revision.
rampitec added a comment.
This revision is now accepted and ready to land.

LGTM with couple comments.



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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:735
+  let AllocationPriority = numRegs;
+  let Weight = numRegs;
 }
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Do you mind to add "let GeneratePressureSet = 0" here before submission?


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:756
+def AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64], (add AGPR_128)>;
+def AReg_512 : ARegClass<16, [v16i32, v16f32], (add AGPR_512)>;
+def AReg_1024 : ARegClass<32, [v32i32, v32f32], (add AGPR_1024)>;
----------------
You will need to rebase since you have added more classes by now.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78553/new/

https://reviews.llvm.org/D78553





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