[PATCH] D78318: [GlobalISel][InlineAsm] Add support for basic output operand constraints

[Konstantin Schwarz via Phabricator via llvm-commits]

kschwarz added inline comments.


================
Comment at: llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp:133
+
+  for (; NumRegs; --NumRegs, ++I) {
+    assert(I != RC->end() && "Ran out of registers to allocate!");
----------------
arsenm wrote:
> kschwarz wrote:
> > arsenm wrote:
> > > Picking multiple physical registers by scanning through the register class doesn't make any sense to me. I would expect NumRegs > 1 only with a virtual register
> > The LLVM IR reference manual contains the following paragraph:
> > > There is also an “interesting” feature which deserves a bit of explanation: if a register class constraint allocates a register which is too small for the value type operand provided as input, the input value will be split into multiple registers, and all of them passed to the inline asm.
> > 
> > X86 uses this at least with the 'A' register constraint, but there are other targets, too (e.g. ARM uses it to pass 64-bit values in even-odd register pairs).
> With physical registers? Can you add a testcase for this?
I can add a fictitious test for AArch64, but it doesn't have asm template argument modifiers to access the "higher" register.
ARM has test cases for this (for SelectionDAG though) here: https://github.com/llvm/llvm-project/blob/master/llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll#L291 


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https://reviews.llvm.org/D78318